RS-new: use CirCularQueuePtr

src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala

@@ -61,7 +61,7 @@ class ReservationStationCtrl
   feedback: Boolean,
   fixedDelay: Int,
   replayDelay: Int = 10
-) extends XSModule {
+) extends XSModule with HasCircularQueuePtrHelper {
 
   val iqSize = IssQueSize
   val iqIdxWidth = log2Up(iqSize)
@@ -95,7 +95,8 @@ class ReservationStationCtrl
   val cntQueue      = Reg(Vec(iqSize, UInt(log2Up(replayDelay).W)))
 
   // rs queue part:
-  val tailPtr       = RegInit(0.U((iqIdxWidth+1).W))
+  // val tailPtr       = RegInit(0.U((iqIdxWidth+1).W))
+  val tailPtr       = RegInit(0.U.asTypeOf(new CircularQueuePtr(iqSize)))
   val idxQueue      = RegInit(VecInit((0 until iqSize).map(_.U(iqIdxWidth.W))))
   val readyQueue    = VecInit(srcQueue.zip(validQueue).map{ case (a,b) => Cat(a).andR & b })
 
@@ -133,7 +134,7 @@ class ReservationStationCtrl
                               Mux(notBlock, !selectedIdxRegOH(i), true.B)
   )))
   val (firstBubble, findBubble) = PriorityEncoderWithFlag(bubMask)
-  haveBubble := findBubble && (firstBubble < tailPtr)
+  haveBubble := findBubble && (firstBubble < tailPtr.asUInt)
   val bubValid = haveBubble
   val bubReg = RegNext(bubValid)
   val bubIdxReg = RegNext(firstBubble - moveMask(firstBubble))
@@ -204,7 +205,7 @@ class ReservationStationCtrl
 
   // enq
   val tailAfterRealDeq = tailPtr - (issFire && !needFeedback|| bubReg)
-  val isFull = tailAfterRealDeq.head(1).asBool() // tailPtr===qsize.U
+  val isFull = tailAfterRealDeq.flag // tailPtr===qsize.U
   tailPtr := tailAfterRealDeq + io.enqCtrl.fire()
 
   io.enqCtrl.ready := !isFull && !io.redirect.valid // TODO: check this redirect && need more optimization
@@ -213,7 +214,7 @@ class ReservationStationCtrl
   val srcTypeSeq  = Seq(enqUop.ctrl.src1Type, enqUop.ctrl.src2Type, enqUop.ctrl.src3Type)
   val srcStateSeq = Seq(enqUop.src1State, enqUop.src2State, enqUop.src3State)
 
-  val enqIdx_ctrl = tailAfterRealDeq.tail(1)
+  val enqIdx_ctrl = tailAfterRealDeq.value
   val enqBpVec = io.data.srcUpdate(IssQueSize)
 
   def stateCheck(src: UInt, srcType: UInt): Bool = {
@@ -245,19 +246,19 @@ class ReservationStationCtrl
   }
 
   // other to Data
-  io.data.enqPtr := idxQueue(Mux(tailPtr.head(1).asBool, deqIdx, tailPtr.tail(1)))
+  io.data.enqPtr := idxQueue(Mux(tailPtr.flag, deqIdx, tailPtr.value))
   io.data.deqPtr.valid  := selValid
   io.data.deqPtr.bits   := idxQueue(selectedIdxWire)
   io.data.enqCtrl.valid := io.enqCtrl.fire
   io.data.enqCtrl.bits  := io.enqCtrl.bits
 
   // other io
-  io.numExist := tailPtr
+  io.numExist := Mux(tailPtr.flag, (iqSize-1).U, tailPtr.value) // NOTE: numExist is iqIdxWidth.W, maybe a bug
 
   // assert
-  assert(RegNext(tailPtr <= iqSize.U))
+  assert(RegNext(Mux(tailPtr.flag, tailPtr.value===0.U, true.B)))
 
-  val print = !(tailPtr===0.U) || io.enqCtrl.valid
+  val print = !(tailPtr.asUInt===0.U) || io.enqCtrl.valid
   XSDebug(print || true.B, p"In(${io.enqCtrl.valid} ${io.enqCtrl.ready}) Out(${issValid} ${io.data.fuReady})\n")
   XSDebug(print , p"tailPtr:${tailPtr} tailPtrAdq:${tailAfterRealDeq} isFull:${isFull} " +
     p"needFeed:${needFeedback} vQue:${Binary(VecInit(validQueue).asUInt)} rQue:${Binary(readyQueue.asUInt)}\n")