- 18 1月, 2022 1 次提交
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由 Lingrui98 提交于
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- 17 1月, 2022 3 次提交
- 16 1月, 2022 1 次提交
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由 Li Qianruo 提交于
Rocket's Debug Module uses unaligned Get and Put to access physical memory. However, our non-inclusive L3 does not have very good support for non-aligned Puts and Gets, so here 256-bit aligned PutPartial and Get is used. Currently on every request, only 1 byte of data is stored using mask, and only one byte of loaded data is used, because otherwise it would require a lot more modification to Rocket's code. Note that this feature is currently only usable with DefaultConfig.
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- 15 1月, 2022 1 次提交
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由 wakafa 提交于
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- 14 1月, 2022 5 次提交
- 13 1月, 2022 4 次提交
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 zhanglinjuan 提交于
* dcache: fix bug that a block could be released twice * MainPipe: fix bug in way_en of miss_req * MainPipe: fix bug
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- 12 1月, 2022 2 次提交
- 11 1月, 2022 1 次提交
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由 JinYue 提交于
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- 10 1月, 2022 1 次提交
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由 Steve Gou 提交于
bump bpu timing
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- 09 1月, 2022 3 次提交
- 08 1月, 2022 3 次提交
- 07 1月, 2022 11 次提交
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由 Lingrui98 提交于
* remove base table and use ftb results as base pred * add corrsponding redirect logic in bpu
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由 JinYue 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
* split entries into by numBr and use bits in pc to hash between them * use shorter tags for each table * make perfEvents a general interface for branch predictor components in order to remove casting operation in composer
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由 William Wang 提交于
ecc tag error should not be reported if we do not read tag
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由 William Wang 提交于
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由 Li Qianruo 提交于
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由 Li Qianruo 提交于
Previously the stepie bit won't take effect
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由 Jiawei Lin 提交于
* l2/l3: Report ecc error to beu or plic * Bump huancun * Connect l3 ecc error to plic
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由 Jiawei Lin 提交于
* SoC: Use TLBuffer instead TLEdgeBuffer * Buffer adjustment
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由 Yinan Xu 提交于
CSRs are updated later after instructions commit from ROB. Thus, we need to delay difftest commit for several cycles.
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- 06 1月, 2022 4 次提交