- 26 3月, 2021 2 次提交
- 25 3月, 2021 4 次提交
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由 Allen 提交于
XSPerfAccumulate: sum up performance values. XSPerfHistogram: count the occurrence of performance values, split them into bins, so that we can estimate their distribution. XSPerfMax: get max of performance values.
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由 Allen 提交于
Not tested yet. Added: * L1 MSHR occupation * L1 MSHR latency * L1 Load Miss latency * L1 Store latency * L1 Store occupation * L1 Load req count
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由 Allen 提交于
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由 Allen 提交于
Now we can put a performance value into several bins and count them. In this way, we can get a distribution of this performance value.
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- 24 3月, 2021 3 次提交
- 23 3月, 2021 1 次提交
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由 Yinan Xu 提交于
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- 22 3月, 2021 8 次提交
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由 Yinan Xu 提交于
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由 ljw 提交于
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由 Yinan Xu 提交于
Update SoC and emu configurations
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
Add bus error unit and connect ecc errors to beu
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由 zhanglinjuan 提交于
* MissQueue: add perf cnt for inflight entries in maximum * MissQueue: max_inflight ignores cycles when missQueue is empty
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由 Lemover 提交于
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- 21 3月, 2021 1 次提交
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由 Yinan Xu 提交于
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- 20 3月, 2021 1 次提交
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由 Yinan Xu 提交于
This allows the software to determine whether an address can be read or written.
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- 19 3月, 2021 8 次提交
- 18 3月, 2021 2 次提交
- 14 3月, 2021 1 次提交
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由 Steve Gou 提交于
* add perf counters for btb and ubtb * update btb only on not hit or jalr mispredicts to reduce write stalls
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- 13 3月, 2021 3 次提交
- 12 3月, 2021 3 次提交
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由 Lemover 提交于
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由 zhanglinjuan 提交于
* DCacheWrapper: MainPipe use read port 1 to ease congestion * MainPipe: do not consider congestion with ldu0 read when disabling fast wakeup
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由 Lemover 提交于
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- 11 3月, 2021 3 次提交
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由 Yinan Xu 提交于
Previously we use numactl to specify both nodes and cpus for emu. However, when other processes are using the same cpu, verilated emu suffers from huge performance degradation. To avoid these scenarios, we only specify the numa node to achieve a more stable performance.
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由 Yinan Xu 提交于
In this commit, we add support for a simpler version of move elimination. The original instruction sequences are: move r1, r0 add r2, r1, r3 The optimized sequnces are: move pr1, pr0 add pr2, pr0, pr3 # instead of add pr2, pr1, pr3 In this way, add can be issued once r0 is ready and move seems to be eliminated.
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由 Yinan Xu 提交于
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