ecc tag error should not be reported if we do not read tag

Previously the stepie bit won't take effect

* l2/l3: Report ecc error to beu or plic

* Bump huancun

* Connect l3 ecc error to plic

* SoC: Use TLBuffer instead TLEdgeBuffer

* Buffer adjustment

CSRs are updated later after instructions commit from ROB. Thus, we
need to delay difftest commit for several cycles.

* Reduce trigger hit wires that goes into exceptiongen
* Fix frontend triggers rewriting hit wire
* Retrieved some accidentally dropped changes in branch dm-debug (mainly fixes to debug mode)
* Fix dmode in tdata1
* Fix ebreaks not causing exception in debug mode
* Fix dcsr field bugs
* Fix faulty distributed tEnable
* Fix store triggers not using vaddr
* Fix store trigger rewriting hit vector
* Initialize distributed tdata registers in MemBlock and Frontend to zero
* Fix load trigger select bit in mcontrol
* Fix singlestep bit valid in debug mode
* Mask all interrupts in debug mode

trigger: add reset value of distribute trigger csrs at memory and frontend block

* mem: fix error csr update

* dcache: l2 error will now trigger atom error

* chore: fix cache error debug decoder

* mem: split L1CacheErrorInfo and L1BusErrorUnitInfo

XiangShan has registered an marchid of 25: https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md .
This value should be returned from CSR `marchid`.

* fix performance counter in ICacheMainpipe

* IPrefetch: add prefetch address merge and counter

* Add Prefetch and Parity enable register for ICache

* Add ICache parity enable control for pipe

* IFU: fix mmio RVC bug

* IFU: add resend address check for mmio

When a mmio fetch an RVI instruction which cross 64 bits,
IFU must send paddr + 2.U to fetch the higher 16 bits.
But the paddr + 2.U is not checked by TLB or PMP. This may cause
some unexpected fetch stuck problem.

This commit adds blocking logic for instructions when they enter
dispatch queues. If previous instructions have exceptions, any
following instructions should be enter dispatch queue.

Consider the following case. If uop(0) has an exception and is a load.
If uop(1) does not have an exception and is a load as well. Then the
allocation logic in dispatch queue will allocate an entry for both
uop(0) and uop(1). However, uop(0) will not set enq.valid and leave
the entry in dispatch queue empty. uop(1) will be allocated in dpq.
In dispatch queue, pointers are updated according to the real number
of instruction enqueue, which is one. While the second is actually
allocated. This causes errors.

* bump huancun

* Fix probe BtoB
Co-authored-by: NLinJiawei <linjiawei20s@ict.ac.cn>

* dcache: add source info in L1CacheErrorInfo

* ICache: fix valid signal and add source/opType

* dcache: fix bug in ecc error

* mem,csr: send full L1CacheErrorInfo to CSR

* icache: provide cache error info for CSR

* dcache: force resp hit if tag ecc error happens

* mem: reorg l1 cache error report path

Now dcache tag error will force trigger a hit

* dcache: fix readline ecc check error

* dcache: mainpipe will not be influenced by tag error

* dcache: fix data ecc check error

* dcache: if coh state is Nothing, do not raise error
Co-authored-by: Nzhanglinjuan <zhanglinjuan20s@ict.ac.cn>
Co-authored-by: NJinYue <jinyue20s@ict.ac.cn>

add buffer at tl pma

For 0:x and 1:x, 1:x should be after 0:x.

Valid should be set to true after atomic.exception.valid and cleared
after redirect is valid.

If s2_data_invalid and s2_ldld_violation happens together, enter
s2_ldld_violation workflow.

Note:
ld-ld violation or forward failure will let an normal load inst replay
from fetch. If TLB hit and ld-ld violation / forward failure happens,
we write back that inst immediately. Meanwhile, such insts will not be
replayed from rs.

Exception address is used serveral cycles after flush. We delay it
by more cycles to ensure its flush safety.

* IPrefetch: fix prefetchPtr stop problem

* This problem happens because prefetchPtr still exits when close IPrefetch

* Fix PMP req port still be occupied even when ICache miss

* Shut down IPrefetch

* IPrefetch: fix Hint not set PreferCache bit

* bump HuanCun

* mem: optimize missq reject to lq timing

DCache replay request is quite slow to generate, as it need to compare
load address with address in all valid miss queue entries.

Now we delay the usage of replay request from data cache.
Now replay request will not influence normal execution flow until
load_s3 (1 cycle after load_s2, load result writeback to RS).

Note1: It is worth mentioning that "select refilling inst for load
writeback" will be disabled if dcacheRequireReplay in the
last cycle.

Note2: ld-ld violation or forward failure will let an normal load inst replay
from fetch. If TLB hit and ld-ld violation / forward failure happens,
we write back that inst immediately. Meanwhile, such insts will not be
replayed from rs.

* dcache: compare probe block addr instead of full addr

* difftest: bump difftest to support --no-diff test

* ci: add cacheoptest test (--no-diff)

* dcache: use sram to build ecc array

* MainPipe: latch s1_encTag to last until s1_fire
Authored-by: Nzhanglinjuan <zhanglinjuan20s@ict.ac.cn>

This commit adds an LsqEnqCtrl module to add one more clock cycle
between dispatch and load/store queue.

LsqEnqCtrl maintains the lqEnqPtr/sqEnqPtr and lqCounter/sqCounter.
They are used to determine whether load/store queue can accept new
instructions. After that, instructions are sent to load/store queue.
This module decouples queue allocation and real enqueue.

Besides, uop storage in load/store queue are optimized. In dispatch,
only robIdx is required. Other information is naturally conveyed in
the pipeline and can be stored later in load/store queue if needed.
For example, exception vector, trigger, ftqIdx, pdest, etc are
unnecessary before the instruction leaves the load/store pipeline.

This commit removed PriorityEncoder in sbuffer enq path. It should improve sbuffer enqueue timing.

* pma: allow r/w priv for l3-cache op mmio space

* bump huancun

* bump huancun

* bump huancun

* Add Naive Instruction Prefetch

* Add instruction prefetch module in ICache

* send Hint to L2 (prefetched data stores in L2)

* Ftq: add prefetchPtr and prefetch interface

* Fix IPrefetch PMP Port preempting problem

* Fix merge conflict

Refactor Trigger