* move statisical corrector to stage 3
* add recover path in stage 3 for ras in case stage 2 falsely push or pop
* let stage 2 has the highest physical priority in bpu
* left ras broken for the next commit to fix

* timing: use single ported SRAMs, invalidating read responses on write
* performance:
-- shortening history length to accelerate training
-- use a predictor to reduce s2_redirects on FTB not hit

* IPrefetch: fix prefetchPtr stop problem

* This problem happens because prefetchPtr still exits when close IPrefetch

* Fix PMP req port still be occupied even when ICache miss

* Shut down IPrefetch

* IPrefetch: fix Hint not set PreferCache bit

* bump HuanCun

* IPrefetch: fix prefetchPtr stop problem

* This problem happens because prefetchPtr still exits when close IPrefetch

* Fix PMP req port still be occupied even when ICache miss

* Shut down IPrefetch

* IPrefetch: fix Hint not set PreferCache bit

* bump HuanCun

* This problem happens because prefetchPtr still exits when close IPrefetch

* Fix PMP req port still be occupied even when ICache miss

* Add Naive Instruction Prefetch

* Add instruction prefetch module in ICache

* send Hint to L2 (prefetched data stores in L2)

* Ftq: add prefetchPtr and prefetch interface

* Fix IPrefetch PMP Port preempting problem

* Fix merge conflict

This commit adds DelayN(2) to some CSR-related signals, including
control bits to ITLB, DTLB, PTW, etc.

To avoid accessing the ITLB before control bits change, we also need
to delay the flush for two cycles. We assume branch misprediction or
memory violation does not cause csrCtrl to change.

This commit optimizes the coding style and timing for hardware
performance counters.

By default, performance counters are RegNext(RegNext(_)).

* let ubtb store full targets and fall through addresses
* add some fields in BranchPrediction so that ifu requests can be solely derived from it

* decouple fall through address calculating logic from the pftAddr interface
* let ghr update from s1 has the highest priority
* fix the physical priority of PhyPriorityMuxGenerator

bpu: bring folded history into use, and use previous ghr to do difftest; move tage and ittage config to top

* use compressed info to do redirects
* implement folded history class

* IFU: move mmio to f3 and wait commit

* IFU: fix mmio_has_commit condition

* compare FtqPtr to ensure the mmio instruction has been committed

* Uncache fetch : cancel flush when backend redirect

* Add perf counters
* add reg from hpm counter source
* add print perfcounter enable

This PR optimizes out isFused and crossPageIPFFix usages in Rob's DispatchData. They will not be stored in ROB. Now DispatchData has only 38 bits.

* isFused is merged with commitType (2 bits reduced)
* crossPageIPFFix is used only in ExceptionGen (1 bit reduced)
* rename: reduce ldest usages
* decode: set isMove to false if ldest is zero

bp stage of each cfi type

This commit removes flush IO for every module. Flush now re-uses
redirect ports to flush the instructions.

* rename Roq to Rob

* remove trailing whitespaces

* remove unused parameters

This commit adds some simple instruction fusion cases in decode stage.
Currently we only implement instruction pairs that can be fused into
RV64GCB instructions.

Instruction fusions are detected in the decode stage by FusionDecoder.
The decoder checks every two instructions and marks the first
instruction fused if they can be fused into one instruction. The second
instruction is removed by setting the valid field to false.

Simple fusion cases include sh1add, sh2add, sh3add, sexth, zexth, etc.

Currently, ftq in frontend needs every instruction to commit. However,
the second instruction is removed from the pipeline and will not commit.
To solve this issue, we temporarily add more bits to isFused to indicate
the offset diff of the two fused instruction. There are four
possibilities now. This feature may be removed later.

This commit also adds more instruction fusion cases that need changes
in both the decode stage and the funtion units. In this commit, we add
some opcode to the function units and fuse the new instruction pairs
into these new internal uops.

The list of opcodes we add in this commit is shown below:
- szewl1: `slli r1, r0, 32` + `srli r1, r0, 31`
- szewl2: `slli r1, r0, 32` + `srli r1, r0, 30`
- byte2: `srli r1, r0, 8` + `andi r1, r1, 255`
- sh4add: `slli r1, r0, 4` + `add r1, r1, r2`
- sr30add: `srli r1, r0, 30` + `add r1, r1, r2`
- sr31add: `srli r1, r0, 31` + `add r1, r1, r2`
- sr32add: `srli r1, r0, 32` + `add r1, r1, r2`
- oddadd: `andi r1, r0, 1`` + `add r1, r1, r2`
- oddaddw: `andi r1, r0, 1`` + `addw r1, r1, r2`
- orh48: mask off the first 16 bits and or with another operand
         (`andi r1, r0, -256`` + `or r1, r1, r2`)

Furthermore, this commit adds some complex instruction fusion cases to
the decode stage and function units. The complex instruction fusion cases
are detected after the instructions are decoded into uop and their
CtrlSignals are used for instruction fusion detection.

We add the following complex instruction fusion cases:
- addwbyte: addw and mask it with 0xff (extract the first byte)
- addwbit: addw and mask it with 0x1 (extract the first bit)
- logiclsb: logic operation and mask it with 0x1 (extract the first bit)
- mulw7: andi 127 and mulw instructions.
        Input to mul is AND with 0x7f if mulw7 bit is set to true.

* previously we only modify jmpTarget on misprediction, and that's
  because we only use ftb to predict jalr target. However, with the
  presence of an indirect branch predictor, there exists such case
  that an indirect branch is correctly predicted when the target in
  ftb entry is wrong.