- 30 1月, 2023 3 次提交
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由 William Wang 提交于
TODO: ldflow from prefetch to be added to ldflow select logic
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由 William Wang 提交于
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由 William Wang 提交于
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- 29 1月, 2023 8 次提交
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由 William Wang 提交于
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由 William Wang 提交于
Now SMS is the same as f684ed00
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由 LinJiawei 提交于
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由 LinJiawei 提交于
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由 Yinan Xu 提交于
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由 William Wang 提交于
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由 William Wang 提交于
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由 William Wang 提交于
TLB and Huancun conflict fix is not included in this commit
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- 28 1月, 2023 24 次提交
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由 William Wang 提交于
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由 LinJiawei 提交于
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由 William Wang 提交于
This commit update coh check assertion to enable aggressive prefetch miss req / store miss req merge. Previous wrong assertion forbids store req from stoping a previous prefetch For example, consider 2 reqs with the same p address fire in order: 1) A prefetch with alias bit 00 need to change coh state from N->T 2) A store with alias bit 11 need to change coh state from B->T Then prefetch and store miss req will be merged in the same missq entry. Store req (2) should be able to stop prefetch (1) so that a ping-pong process will not start
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由 LinJiawei 提交于
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由 William Wang 提交于
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由 LinJiawei 提交于
Note that Huancun have not been updated in this commit
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由 LinJiawei 提交于
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由 William Wang 提交于
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由 William Wang 提交于
No extra latency introduced
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由 William Wang 提交于
Added meta_prefetch and meta_access related sim perf counter For now, optional dcache meta prefetch and access can be removed safely
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由 William Wang 提交于
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由 LinJiawei 提交于
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由 LinJiawei 提交于
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由 LinJiawei 提交于
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由 LinJiawei 提交于
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由 LinJiawei 提交于
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由 LinJiawei 提交于
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由 LinJiawei 提交于
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由 LinJiawei 提交于
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由 William Wang 提交于
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由 William Wang 提交于
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由 William Wang 提交于
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由 William Wang 提交于
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由 William Wang 提交于
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- 19 1月, 2023 1 次提交
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由 Haoyuan Feng 提交于
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- 18 1月, 2023 1 次提交
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由 Haoyuan Feng 提交于
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- 16 1月, 2023 1 次提交
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由 Haoyuan Feng 提交于
* L2TLB: Add L2TLB Resp Check in difftest * L1TLB: Add L1TLB Resp Check in difftest * L2TLB: Do not Check Resp with difftest when access fault * Update difftest
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- 11 1月, 2023 2 次提交
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由 Guokai Chen 提交于
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由 Haoyuan Feng 提交于
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