Merge pull request #246 from RISCVERS/fixBankedL3

Fix banked l3

block-inclusivecache-sifive @ 6b818366

-Subproject commit 37d27a8f3b7d288c4663eebd8571018357fd827a
+Subproject commit 6b818366f86cd7cb61778ef22789323f9a42423e

src/main/scala/device/AXI4DummySD.scala

@@ -53,7 +53,7 @@ class SDHelper extends BlackBox with HasBlackBoxInline {
 
 class AXI4DummySD
 (
-  address: AddressSet
+  address: Seq[AddressSet]
 )(implicit p: Parameters)
   extends AXI4SlaveModule(address, executable = false) with HasSDConst
 {

src/main/scala/device/AXI4Flash.scala

@@ -8,7 +8,7 @@ import utils._
 
 class AXI4Flash
 (
-  address: AddressSet
+  address: Seq[AddressSet]
 )(implicit p: Parameters)
   extends AXI4SlaveModule(address, executable = false)
 {

src/main/scala/device/AXI4Keyboard.scala

@@ -14,7 +14,7 @@ class KeyboardIO extends Bundle {
 // this Module is not tested
 class AXI4Keyboard
 (
-  address: AddressSet
+  address: Seq[AddressSet]
 )(implicit p: Parameters)
   extends AXI4SlaveModule(address, executable = false, _extra = new KeyboardIO)
 {

src/main/scala/device/AXI4RAM.scala

@@ -5,6 +5,7 @@ import chisel3._
 import chisel3.util._
 import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp, RegionType}
 import xiangshan.HasXSParameter
+import utils.{MaskExpand}
 
 class RAMHelper(memByte: BigInt) extends BlackBox with HasXSParameter {
   val io = IO(new Bundle {
@@ -20,7 +21,7 @@ class RAMHelper(memByte: BigInt) extends BlackBox with HasXSParameter {
 
 class AXI4RAM
 (
-  address: AddressSet,
+  address: Seq[AddressSet],
   memByte: Long,
   useBlackBox: Boolean = false,
   executable: Boolean = true,
@@ -32,27 +33,33 @@ class AXI4RAM
 
   override lazy val module = new AXI4SlaveModuleImp(this){
 
+    val split = beatBytes / 8
+    val bankByte = memByte / split
     val offsetBits = log2Up(memByte)
     val offsetMask = (1 << offsetBits) - 1
 
 
     def index(addr: UInt) = ((addr & offsetMask.U) >> log2Ceil(beatBytes)).asUInt()
 
-    def inRange(idx: UInt) = idx < (memByte / 8).U
+    def inRange(idx: UInt) = idx < (memByte / beatBytes).U
 
     val wIdx = index(waddr) + writeBeatCnt
     val rIdx = index(raddr) + readBeatCnt
     val wen = in.w.fire() && inRange(wIdx)
+    require(beatBytes >= 8)
 
     val rdata = if (useBlackBox) {
-      val mem = Module(new RAMHelper(memByte))
-      mem.io.clk := clock
-      mem.io.rIdx := rIdx
-      mem.io.wIdx := wIdx
-      mem.io.wdata := in.w.bits.data
-      mem.io.wmask := fullMask
-      mem.io.wen := wen
-      mem.io.rdata
+      val mems = (0 until split).map {_ => Module(new RAMHelper(bankByte))}
+      mems.zipWithIndex map { case (mem, i) =>
+        mem.io.clk := clock
+        mem.io.rIdx := (rIdx << log2Up(split)) + i.U
+        mem.io.wIdx := (wIdx << log2Up(split)) + i.U
+        mem.io.wdata := in.w.bits.data((i + 1) * 64 - 1, i * 64)
+        mem.io.wmask := MaskExpand(in.w.bits.strb((i + 1) * 8 - 1, i * 8))
+        mem.io.wen := wen
+      }
+      val rdata = mems.map {mem => mem.io.rdata}
+      Cat(rdata.reverse)
     } else {
       val mem = Mem(memByte / beatBytes, Vec(beatBytes, UInt(8.W)))
 

src/main/scala/device/AXI4SlaveModule.scala

@@ -10,7 +10,7 @@ import xiangshan.HasXSLog
 
 abstract class AXI4SlaveModule[T <: Data]
 (
-  address: AddressSet,
+  address: Seq[AddressSet],
   executable: Boolean = true,
   beatBytes: Int = 8,
   burstLen: Int = 1,
@@ -19,7 +19,7 @@ abstract class AXI4SlaveModule[T <: Data]
 
   val node = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
     Seq(AXI4SlaveParameters(
-      Seq(address),
+      address,
       regionType = RegionType.UNCACHED,
       executable = executable,
       supportsWrite = TransferSizes(1, beatBytes * burstLen),

src/main/scala/device/AXI4Timer.scala

@@ -12,7 +12,7 @@ class TimerIO extends Bundle {
 class AXI4Timer
 (
   sim: Boolean = false,
-  address: AddressSet
+  address: Seq[AddressSet]
 )(implicit p: Parameters)
   extends AXI4SlaveModule(address, executable = false, _extra = new TimerIO)
 {

src/main/scala/device/AXI4UART.scala

@@ -20,7 +20,7 @@ class UARTIO extends Bundle {
 
 class AXI4UART
 (
-  address: AddressSet
+  address: Seq[AddressSet]
 )(implicit p: Parameters)
   extends AXI4SlaveModule(address, executable = false, _extra = new UARTIO)
 {

src/main/scala/device/AXI4VGA.scala

@@ -54,7 +54,7 @@ class VGACtrlBundle extends Bundle {
 
 class VGACtrl
 (
-  address: AddressSet
+  address: Seq[AddressSet]
 )(implicit p: Parameters)
   extends AXI4SlaveModule(address, _extra = new VGACtrlBundle, executable = false) with HasVGAParameter {
   override lazy val module = new AXI4SlaveModuleImp[VGACtrlBundle](this) {
@@ -106,8 +106,8 @@ class FBHelper extends BlackBox with HasBlackBoxInline {
 class AXI4VGA
 (
   sim: Boolean = false,
-  fbAddress: AddressSet,
-  ctrlAddress: AddressSet
+  fbAddress: Seq[AddressSet],
+  ctrlAddress: Seq[AddressSet]
 )(implicit p: Parameters)
   extends LazyModule with HasVGAParameter {
 

src/main/scala/system/SoC.scala

@@ -8,7 +8,11 @@ import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp}
 import freechips.rocketchip.tilelink.{TLBuffer, TLFuzzer, TLIdentityNode, TLXbar}
 import utils.DebugIdentityNode
 import xiangshan.{HasXSParameter, XSCore}
-
+import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, AddressSet}
+import freechips.rocketchip.tilelink.{TLBundleParameters, TLCacheCork, TLBuffer, TLClientNode, TLIdentityNode, TLXbar, TLWidthWidget, TLFilter, TLToAXI4}
+import freechips.rocketchip.devices.tilelink.{TLError, DevNullParams}
+import freechips.rocketchip.amba.axi4.{AXI4ToTL, AXI4IdentityNode, AXI4UserYanker, AXI4Fragmenter, AXI4IdIndexer, AXI4Deinterleaver}
 
 case class SoCParameters
 (
@@ -38,23 +42,94 @@ class DummyCore()(implicit p: Parameters) extends LazyModule {
 
 
 class XSSoc()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
+  val numCores = 1
 
-  private val xsCore = LazyModule(new XSCore())
+  private val cores = Seq.fill(numCores)(LazyModule(new XSCore()))
 
   // only mem and extDev visible externally
-  val mem = xsCore.mem
+  val dma = AXI4IdentityNode()
   val extDev = TLIdentityNode()
 
+  // L2 to L3 network
+  // -------------------------------------------------
+  private val l3_xbar = TLXbar()
+
+  private val l3_banks = (0 until L3NBanks) map (i =>
+      LazyModule(new InclusiveCache(
+        CacheParameters(
+          level = 3,
+          ways = L3NWays,
+          sets = L3NSets,
+          blockBytes = L3BlockSize,
+          beatBytes = L2BusWidth / 8,
+          cacheName = s"L3_$i"
+        ),
+      InclusiveCacheMicroParameters(
+        writeBytes = 8
+      )
+    )))
+
+  cores.foreach(core => l3_xbar := TLBuffer() := DebugIdentityNode() := core.mem)
+
+  // DMA should not go to MMIO
+  val mmioRange = AddressSet(base = 0x0000000000L, mask = 0x007fffffffL)
+  // AXI4ToTL needs a TLError device to route error requests,
+  // add one here to make it happy.
+  val tlErrorParams = DevNullParams(
+    address = Seq(mmioRange),
+    maxAtomic = 8,
+    maxTransfer = 64)
+  val tlError = LazyModule(new TLError(params = tlErrorParams, beatBytes = L2BusWidth / 8))
+  private val tlError_xbar = TLXbar()
+  tlError_xbar :=
+    AXI4ToTL() :=
+    AXI4UserYanker(Some(1)) :=
+    AXI4Fragmenter() :=
+    AXI4IdIndexer(1) :=
+    dma
+  tlError.node := tlError_xbar
+
+  l3_xbar :=
+    TLBuffer() :=
+    DebugIdentityNode() :=
+    tlError_xbar
+
+  def bankFilter(bank: Int) = AddressSet(
+    base = bank * L3BlockSize,
+    mask = ~BigInt((L3NBanks -1) * L3BlockSize))
+
+  for(i <- 0 until L3NBanks) {
+    val filter = TLFilter(TLFilter.mSelectIntersect(bankFilter(i)))
+    l3_banks(i).node := TLBuffer() := DebugIdentityNode() := filter := l3_xbar
+  }
+
+
+  // L3 to memory network
+  // -------------------------------------------------
+  private val memory_xbar = TLXbar()
+
+  val mem = Seq.fill(L3NBanks)(AXI4IdentityNode())
+  for(i <- 0 until L3NBanks) {
+    mem(i) :=
+      AXI4UserYanker() :=
+      TLToAXI4() :=
+      TLWidthWidget(L3BusWidth / 8) :=
+      TLCacheCork() :=
+      l3_banks(i).node
+  }
+
   private val mmioXbar = TLXbar()
   private val clint = LazyModule(new TLTimer(
     Seq(AddressSet(0x38000000L, 0x0000ffffL)),
     sim = !env.FPGAPlatform
   ))
 
-  mmioXbar :=
+  cores.foreach(core =>
+    mmioXbar :=
     TLBuffer() :=
     DebugIdentityNode() :=
-    xsCore.mmio
+    core.mmio
+  )
 
   clint.node :=
     mmioXbar
@@ -67,9 +142,11 @@ class XSSoc()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
       val meip = Input(Bool())
       val ila = if(env.FPGAPlatform && EnableILA) Some(Output(new ILABundle)) else None
     })
-    xsCore.module.io.externalInterrupt.mtip := clint.module.io.mtip
-    xsCore.module.io.externalInterrupt.msip := clint.module.io.msip
-    xsCore.module.io.externalInterrupt.meip := RegNext(RegNext(io.meip))
+    cores.foreach(core => {
+      core.module.io.externalInterrupt.mtip := clint.module.io.mtip
+      core.module.io.externalInterrupt.msip := clint.module.io.msip
+      core.module.io.externalInterrupt.meip := RegNext(RegNext(io.meip))
+    })
   }
 
 }

src/main/scala/xiangshan/XSCore.scala

@@ -11,9 +11,11 @@ import xiangshan.mem._
 import xiangshan.backend.fu.HasExceptionNO
 import xiangshan.cache.{ICache, DCache, L1plusCache, DCacheParameters, ICacheParameters, L1plusCacheParameters, PTW, Uncache}
 import chipsalliance.rocketchip.config
-import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
-import freechips.rocketchip.tilelink.{TLBundleParameters, TLCacheCork, TLBuffer, TLClientNode, TLIdentityNode, TLXbar}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, AddressSet}
+import freechips.rocketchip.tilelink.{TLBundleParameters, TLCacheCork, TLBuffer, TLClientNode, TLIdentityNode, TLXbar, TLWidthWidget, TLFilter, TLToAXI4}
+import freechips.rocketchip.devices.tilelink.{TLError, DevNullParams}
 import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters}
+import freechips.rocketchip.amba.axi4.{AXI4ToTL, AXI4IdentityNode, AXI4UserYanker, AXI4Fragmenter, AXI4IdIndexer, AXI4Deinterleaver}
 import utils._
 
 case class XSCoreParameters
@@ -169,8 +171,6 @@ trait HasXSParameter {
   val PtwL2EntrySize = core.PtwL2EntrySize
   val NumPerfCounters = core.NumPerfCounters
 
-  val l1BusDataWidth = 256
-
   val icacheParameters = ICacheParameters(
     nMissEntries = 2
   )
@@ -190,6 +190,28 @@ trait HasXSParameter {
   )
 
   val LRSCCycles = 100
+
+
+  // cache hierarchy configurations
+  val l1BusDataWidth = 256
+
+  // L2 configurations
+  val L1BusWidth = 256
+  val L2Size = 512 * 1024 // 512KB
+  val L2BlockSize = 64
+  val L2NWays = 8
+  val L2NSets = L2Size / L2BlockSize / L2NWays
+
+  // L3 configurations
+  val L2BusWidth = 256
+  val L3Size = 4 * 1024 * 1024 // 4MB
+  val L3BlockSize = 64
+  val L3NBanks = 4
+  val L3NWays = 8
+  val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays
+
+  // on chip network configurations
+  val L3BusWidth = 256
 }
 
 trait HasXSLog { this: RawModule =>
@@ -240,39 +262,42 @@ object AddressSpace extends HasXSParameter {
 
 
 
-class XSCore()(implicit p: config.Parameters) extends LazyModule {
+class XSCore()(implicit p: config.Parameters) extends LazyModule with HasXSParameter {
 
+  // inner nodes
   val dcache = LazyModule(new DCache())
   val uncache = LazyModule(new Uncache())
   val l1pluscache = LazyModule(new L1plusCache())
   val ptw = LazyModule(new PTW())
 
+  // out facing nodes
   val mem = TLIdentityNode()
   val mmio = uncache.clientNode
 
-  // TODO: refactor these params
+  // L1 to L2 network
+  // -------------------------------------------------
+  private val l2_xbar = TLXbar()
+
   private val l2 = LazyModule(new InclusiveCache(
     CacheParameters(
       level = 2,
-      ways = 4,
-      sets = 512 * 1024 / (64 * 4),
-      blockBytes = 64,
-      beatBytes = 32 // beatBytes = l1BusDataWidth / 8
+      ways = L2NWays,
+      sets = L2NSets,
+      blockBytes = L2BlockSize,
+      beatBytes = L1BusWidth / 8, // beatBytes = l1BusDataWidth / 8
+      cacheName = s"L2"
     ),
     InclusiveCacheMicroParameters(
       writeBytes = 8
     )
   ))
 
-  private val xbar = TLXbar()
-
-  xbar := TLBuffer() := DebugIdentityNode() := dcache.clientNode
-  xbar := TLBuffer() := DebugIdentityNode() := l1pluscache.clientNode
-  xbar := TLBuffer() := DebugIdentityNode() := ptw.node
-
-  l2.node := xbar
+  l2_xbar := TLBuffer() := DebugIdentityNode() := dcache.clientNode
+  l2_xbar := TLBuffer() := DebugIdentityNode() := l1pluscache.clientNode
+  l2_xbar := TLBuffer() := DebugIdentityNode() := ptw.node
+  l2.node := TLBuffer() := DebugIdentityNode() := l2_xbar
 
-  mem := TLBuffer() := TLCacheCork() := TLBuffer() := l2.node
+  mem := l2.node
 
   lazy val module = new XSCoreImp(this)
 }

src/test/scala/cache/L1plusCacheTest.scala

@@ -51,7 +51,7 @@ class L1plusTestTop()(implicit p: Parameters) extends LazyModule{
   ))
 
   val ram = LazyModule(new AXI4RAM(
-    AddressSet(0x0L, 0xffffffffffL),
+    Seq(AddressSet(0x0L, 0xffffffffffL)),
     memByte = 128 * 1024 * 1024,
     useBlackBox = false
   ))

src/test/scala/cache/L2CacheNonInclusiveGetTest.scala

@@ -52,7 +52,7 @@ class L2NonInclusiveGetTestTop()(implicit p: Parameters) extends LazyModule {
       beatBytes = 8))))
 
   val ram = LazyModule(new AXI4RAM(
-    AddressSet(0x0L, 0x7ffffffL),
+    Seq(AddressSet(0x0L, 0x7ffffffL)),
     memByte = 128 * 1024 * 1024,
     useBlackBox = false
   ))

src/test/scala/cache/L2CacheTest.scala

@@ -101,7 +101,7 @@ class L2TestTop()(implicit p: Parameters) extends LazyModule{
   ))
 
   val ram = LazyModule(new AXI4RAM(
-    AddressSet(0x0L, 0xffffffffffL),
+    Seq(AddressSet(0x0L, 0xffffffffffL)),
     memByte = 128 * 1024 * 1024,
     useBlackBox = false
   ))

src/test/scala/device/AXI4RamTest.scala

@@ -20,7 +20,7 @@ class AXI4RamFuzzTest()(implicit p: Parameters) extends LazyModule {
     inFlight = 10
   ))
   val ident = LazyModule(new DebugIdentityNode())
-  val axiRam = LazyModule(new AXI4RAM(addressSet, memByte = 1024))
+  val axiRam = LazyModule(new AXI4RAM(Seq(addressSet), memByte = 1024))
 
   axiRam.node :=
     AXI4UserYanker() :=
@@ -39,7 +39,7 @@ class AXI4RamBurstTest()(implicit p: Parameters) extends LazyModule {
 
   val addressSet = AddressSet(0x38000000L, 0x0000ffffL)
   val burst = LazyModule(new AXI4BurstMaster(startAddr = addressSet.base.toLong, nOp = 3))
-  val axiRam = LazyModule(new AXI4RAM(addressSet, memByte = 1024))
+  val axiRam = LazyModule(new AXI4RAM(Seq(addressSet), memByte = 1024))
 
   axiRam.node := burst.node
 
@@ -56,7 +56,7 @@ class AXI4RamTLBurstTest()(implicit p: Parameters) extends LazyModule {
 
   val tlburst = LazyModule(new TLBurstMaster(startAddr = addressSet.base.toLong, nOp = 1, burstLen = 32))
   val ident = LazyModule(new DebugIdentityNode())
-  val axiRam = LazyModule(new AXI4RAM(addressSet, memByte = 1024))
+  val axiRam = LazyModule(new AXI4RAM(Seq(addressSet), memByte = 1024))
 
   axiRam.node :=
     AXI4UserYanker() :=

src/test/scala/device/AXI4TimerTest.scala

@@ -16,7 +16,7 @@ class AXI4TimerTestTop(implicit p: Parameters) extends LazyModule {
   val addressSet = AddressSet(0x38000000L, 0x0000ffffL)
   val fuzz = LazyModule(new TLFuzzer(nOperations = 10, overrideAddress = Some(addressSet), inFlight = 1))
   val ident = LazyModule(new DebugIdentityNode())
-  val axiTimer = LazyModule(new AXI4Timer(sim = true, addressSet))
+  val axiTimer = LazyModule(new AXI4Timer(sim = true, Seq(addressSet)))
 
   axiTimer.node :=
     AXI4UserYanker() :=

src/test/scala/top/SimMMIO.scala

@@ -9,14 +9,14 @@ import freechips.rocketchip.tilelink.{TLErrorEvaluator, TLMasterParameters, TLXb
 
 class SimMMIO()(implicit p: config.Parameters) extends LazyModule {
 
-  val uart = LazyModule(new AXI4UART(AddressSet(0x40600000L, 0xf)))
+  val uart = LazyModule(new AXI4UART(Seq(AddressSet(0x40600000L, 0xf))))
   val vga = LazyModule(new AXI4VGA(
     sim = false,
-    fbAddress = AddressSet(0x50000000L, 0x3fffffL),
-    ctrlAddress = AddressSet(0x40001000L, 0x7L)
+    fbAddress = Seq(AddressSet(0x50000000L, 0x3fffffL)),
+    ctrlAddress = Seq(AddressSet(0x40001000L, 0x7L))
   ))
-  val flash = LazyModule(new AXI4Flash(AddressSet(0x40000000L, 0xfff)))
-  val sd = LazyModule(new AXI4DummySD(AddressSet(0x40002000L, 0xfff)))
+  val flash = LazyModule(new AXI4Flash(Seq(AddressSet(0x40000000L, 0xfff))))
+  val sd = LazyModule(new AXI4DummySD(Seq(AddressSet(0x40002000L, 0xfff))))
 
   val axiBus = AXI4Xbar()
 

src/test/scala/top/XSSim.scala

@@ -6,9 +6,9 @@ import chisel3.util._
 import chipsalliance.rocketchip.config
 import chisel3.stage.ChiselGeneratorAnnotation
 import device._
-import freechips.rocketchip.amba.axi4.{AXI4Fragmenter, AXI4UserYanker}
+import freechips.rocketchip.amba.axi4.{AXI4UserYanker, AXI4Xbar}
 import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, LazyModule, LazyModuleImp}
-import freechips.rocketchip.tilelink.{TLBuffer, TLCacheCork, TLFragmenter, TLFuzzer, TLToAXI4, TLXbar}
+import freechips.rocketchip.tilelink.{TLToAXI4}
 import xiangshan._
 import utils._
 import ExcitingUtils.Debug
@@ -66,23 +66,42 @@ class TrapIO extends XSBundle {
 
 class XSSimTop()(implicit p: config.Parameters) extends LazyModule {
 
-  val memAddressSet = AddressSet(0x0L, 0xffffffffffL)
+  // address space[0G - 1024G)
+  val fullRange = AddressSet(0x0L, 0xffffffffffL)
+  // MMIO address space[0G - 2G)
+  val mmioRange = AddressSet(base = 0x0000000000L, mask = 0x007fffffffL)
+  // DRAM address range[2G - 1024G)
+  val dramRange = fullRange.subtract(mmioRange)
+
+  val L3BusWidth = 256
+  val L3BlockSize = 512
 
   val soc = LazyModule(new XSSoc())
+  // AXIRam
+  // -----------------------------------
   val axiRam = LazyModule(new AXI4RAM(
-    memAddressSet,
+    dramRange,
     memByte = 128 * 1024 * 1024,
-    useBlackBox = true
+    useBlackBox = true,
+    beatBytes = L3BusWidth / 8
   ))
-  val axiMMIO = LazyModule(new SimMMIO())
 
+  val xbar = AXI4Xbar()
+  soc.mem.map{mem => xbar := mem}
   axiRam.node :=
-    AXI4UserYanker() :=
-    TLToAXI4() :=
-    TLBuffer(BufferParams.default) :=
-    DebugIdentityNode() :=
-    soc.mem
-
+    xbar
+
+  // AXI DMA
+  // -----------------------------------
+  val burst = LazyModule(new AXI4BurstMaster(
+    startAddr = 0x80000000L,
+    nOp = 0,
+    beatBytes = L3BusWidth / 8))
+  soc.dma := burst.node
+
+  // AXI MMIO
+  // -----------------------------------
+  val axiMMIO = LazyModule(new SimMMIO())
   axiMMIO.axiBus :=
     AXI4UserYanker() :=
     TLToAXI4() :=