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fda42022
编写于
7月 01, 2020
作者:
Z
zhanglinjuan
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
add bpu update signals in redirect bundle
上级
d4e1f99e
变更
6
隐藏空白更改
内联
并排
Showing
6 changed file
with
40 addition
and
13 deletion
+40
-13
src/main/scala/xiangshan/Bundle.scala
src/main/scala/xiangshan/Bundle.scala
+16
-0
src/main/scala/xiangshan/backend/brq/Brq.scala
src/main/scala/xiangshan/backend/brq/Brq.scala
+6
-1
src/main/scala/xiangshan/backend/exu/Alu.scala
src/main/scala/xiangshan/backend/exu/Alu.scala
+4
-0
src/main/scala/xiangshan/frontend/BPU.scala
src/main/scala/xiangshan/frontend/BPU.scala
+4
-11
src/main/scala/xiangshan/frontend/FakeIFU.scala
src/main/scala/xiangshan/frontend/FakeIFU.scala
+3
-1
src/main/scala/xiangshan/frontend/Ibuffer.scala
src/main/scala/xiangshan/frontend/Ibuffer.scala
+7
-0
未找到文件。
src/main/scala/xiangshan/Bundle.scala
浏览文件 @
fda42022
...
...
@@ -10,12 +10,14 @@ class FetchPacket extends XSBundle {
val
instrs
=
Vec
(
FetchWidth
,
UInt
(
32.
W
))
val
mask
=
UInt
((
FetchWidth
*
2
).
W
)
val
pc
=
UInt
(
VAddrBits
.
W
)
// the pc of first inst in the fetch group
val
pnpc
=
Vec
(
FetchWidth
,
UInt
(
VAddrBits
.
W
))
}
// Dequeue DecodeWidth insts from Ibuffer
class
CtrlFlow
extends
XSBundle
{
val
instr
=
UInt
(
32.
W
)
val
pc
=
UInt
(
VAddrBits
.
W
)
val
pnpc
=
UInt
(
VAddrBits
.
W
)
val
exceptionVec
=
Vec
(
16
,
Bool
())
val
intrVec
=
Vec
(
12
,
Bool
())
val
isRVC
=
Bool
()
...
...
@@ -55,13 +57,27 @@ class MicroOp extends CfCtrl {
}
class
Redirect
extends
XSBundle
{
val
pc
=
UInt
(
VAddrBits
.
W
)
// wrongly predicted pc
val
target
=
UInt
(
VAddrBits
.
W
)
val
brTag
=
UInt
(
BrTagWidth
.
W
)
val
_type
=
UInt
(
2.
W
)
val
taken
=
Bool
()
val
isException
=
Bool
()
val
roqIdx
=
UInt
(
ExtendedRoqIdxWidth
.
W
)
val
freelistAllocPtr
=
new
FreeListPtr
}
// class BpuUpdateReq extends XSBundle {
// val pc = UInt(VAddrBits.W)
// val isMissPred = Bool()
// val _type = UInt(2.W)
// val actualTarget = UInt(VAddrBits.W)
// val actualTaken = Bool()
// val redirect = new Redirect
// TODO:
// val isRVC = Bool()
//}
class
Dp1ToDp2IO
extends
XSBundle
{
val
intDqToDp2
=
Vec
(
IntDqDeqWidth
,
DecoupledIO
(
new
MicroOp
))
val
fpDqToDp2
=
Vec
(
FpDqDeqWidth
,
DecoupledIO
(
new
MicroOp
))
...
...
src/main/scala/xiangshan/backend/brq/Brq.scala
浏览文件 @
fda42022
...
...
@@ -24,8 +24,10 @@ class Brq extends XSModule {
})
class
BrqEntry
extends
Bundle
{
// val pc = UInt(VAddrBits.W)
val
npc
=
UInt
(
VAddrBits
.
W
)
val
redirect
=
new
Redirect
// val _type = UInt(2.W)
}
val
brQueue
=
Reg
(
Vec
(
BrqSize
,
new
BrqEntry
))
...
...
@@ -62,7 +64,10 @@ class Brq extends XSModule {
enq
.
ready
:=
!
full
brTag
:=
tailIdx
// TODO: check rvc and use predict npc
when
(
enq
.
fire
()){
brQueue
(
tailIdx
).
npc
:=
enq
.
bits
.
cf
.
pc
+
4.
U
}
// when(enq.fire()){ brQueue(tailIdx).npc := enq.bits.cf.pc + 4.U }
when
(
enq
.
fire
())
{
brQueue
(
tailIdx
).
npc
:=
enq
.
bits
.
cf
.
pnpc
}
brMaskNext
=
brMaskNext
|
Mux
(
enq
.
fire
(),
UIntToOH
(
tailIdx
),
0.
U
)
brMask
:=
brMaskNext
tailPtrNext
=
tailPtrNext
+
enq
.
fire
()
...
...
src/main/scala/xiangshan/backend/exu/Alu.scala
浏览文件 @
fda42022
...
...
@@ -6,6 +6,7 @@ import xiangshan._
import
xiangshan.FuType._
import
xiangshan.utils._
import
xiangshan.backend.regfile.RfWritePort
import
xiangshan.backend.decode.isa.RV32I_BRUInstr
object
ALUOpType
{
def
add
=
"b000000"
.
U
...
...
@@ -100,8 +101,11 @@ class Alu extends Exu(alu.litValue()) {
io
.
in
.
ready
:=
io
.
out
.
ready
val
pcLatchSlot
=
Mux
(
isRVC
,
pc
+
2.
U
,
pc
+
4.
U
)
io
.
out
.
bits
.
redirect
.
valid
:=
io
.
out
.
valid
&&
isBru
//isBranch
io
.
out
.
bits
.
redirect
.
bits
.
pc
:=
uop
.
cf
.
pc
io
.
out
.
bits
.
redirect
.
bits
.
target
:=
Mux
(!
taken
&&
isBranch
,
pcLatchSlot
,
target
)
io
.
out
.
bits
.
redirect
.
bits
.
brTag
:=
uop
.
brTag
io
.
out
.
bits
.
redirect
.
bits
.
_type
:=
LookupTree
(
func
,
RV32I_BRUInstr
.
bruFuncTobtbTypeTable
)
io
.
out
.
bits
.
redirect
.
bits
.
taken
:=
taken
io
.
out
.
bits
.
redirect
.
bits
.
isException
:=
DontCare
// false.B
io
.
out
.
bits
.
redirect
.
bits
.
roqIdx
:=
uop
.
roqIdx
io
.
out
.
bits
.
redirect
.
bits
.
freelistAllocPtr
:=
uop
.
freelistAllocPtr
...
...
src/main/scala/xiangshan/frontend/BPU.scala
浏览文件 @
fda42022
...
...
@@ -21,14 +21,15 @@ class TableAddr(val idxBits: Int, val banks: Int) extends XSBundle {
class
BPU
extends
XSModule
{
val
io
=
IO
(
new
Bundle
()
{
val
flush
=
Input
(
Bool
())
// val flush = Input(Bool())
// update bpu based on redirect signals from brq
val
redirect
=
Flipped
(
ValidIO
(
new
Redirect
))
val
in
=
new
Bundle
{
val
pc
=
Flipped
(
Valid
(
UInt
(
VAddrBits
.
W
)))
}
// val out = new Bundle { val redirect = Valid(UInt(VAddrBits.W)) }
val
predMask
=
Output
(
Vec
(
FetchWidth
,
Bool
()))
val
predTargets
=
Output
(
Vec
(
FetchWidth
,
UInt
(
VAddrBits
.
W
)))
})
val
flush
=
BoolStopWatch
(
io
.
flush
,
io
.
in
.
pc
.
valid
,
startHighPriority
=
true
)
val
flush
=
BoolStopWatch
(
io
.
redirect
.
valid
,
io
.
in
.
pc
.
valid
,
startHighPriority
=
true
)
// BTB makes a quick prediction for branch and direct jump, which is
// 4-way set-associative, and each way is divided into 4 banks.
...
...
@@ -117,14 +118,6 @@ class BPU extends XSModule {
}
// redirect based on BTB and JBTAC
/*
val redirectMask = Wire(Vec(FetchWidth, Bool()))
val redirectTarget = Wire(Vec(FetchWidth, UInt(VAddrBits.W)))
(0 until FetchWidth).map(i => redirectMask(i) := btbHits(i) && Mux(btbTypes(i) === BTBtype.B, btbTakens(i), true.B) || jbtacHits(i))
(0 until FetchWidth).map(i => redirectTarget(i) := Mux(btbHits(i) && !(btbTypes(i) === BTBtype.B && !btbTakens(i)), btbTargets(i), jbtacTargets(i)))
io.out.redirect.valid := redirectMask.asUInt.orR
io.out.redirect.bits := PriorityMux(redirectMask, redirectTarget)
*/
(
0
until
FetchWidth
).
map
(
i
=>
io
.
predMask
(
i
)
:=
btbHits
(
i
)
&&
Mux
(
btbTypes
(
i
)
===
BTBtype
.
B
,
btbTakens
(
i
),
true
.
B
)
||
jbtacHits
(
i
))
(
0
until
FetchWidth
).
map
(
i
=>
io
.
predTargets
(
i
)
:=
Mux
(
btbHits
(
i
)
&&
!(
btbTypes
(
i
)
===
BTBtype
.
B
&&
!
btbTakens
(
i
)),
btbTargets
(
i
),
jbtacTargets
(
i
)))
...
...
src/main/scala/xiangshan/frontend/FakeIFU.scala
浏览文件 @
fda42022
...
...
@@ -66,7 +66,8 @@ class FakeIFU extends XSModule with HasIFUConst {
// val npc = Mux(io.redirect.valid, io.redirect.bits.target, snpc) // next pc
val
npc
=
Mux
(
io
.
redirect
.
valid
,
io
.
redirect
.
bits
.
target
,
Mux
(
predRedirect
,
predTarget
,
snpc
))
bpu
.
io
.
flush
:=
io
.
fetchPacket
.
fire
()
// bpu.io.flush := io.redirect.valid
bpu
.
io
.
redirect
:=
io
.
redirect
bpu
.
io
.
in
.
pc
.
valid
:=
io
.
fetchPacket
.
fire
()
bpu
.
io
.
in
.
pc
.
bits
:=
npc
...
...
@@ -81,6 +82,7 @@ class FakeIFU extends XSModule with HasIFUConst {
io
.
fetchPacket
.
bits
.
mask
:=
Fill
(
FetchWidth
*
2
,
1.
U
(
1.
W
))
<<
pc
(
2
+
log2Up
(
FetchWidth
)-
1
,
1
)
io
.
fetchPacket
.
bits
.
pc
:=
pc
io
.
fetchPacket
.
bits
.
instrs
:=
fakeCache
.
io
.
rdata
io
.
fetchPacket
.
bits
.
pnpc
:=
bpu
.
io
.
predTargets
Debug
(
cond
=
io
.
fetchPacket
.
fire
()){
printf
(
p
"==========FetchGroup==========\nfirst pc:${Hexadecimal(pc)}\n"
)
...
...
src/main/scala/xiangshan/frontend/Ibuffer.scala
浏览文件 @
fda42022
...
...
@@ -27,6 +27,7 @@ class Ibuffer extends XSModule {
// ibuf define
val
ibuf
=
Reg
(
Vec
(
IBufSize
*
2
,
UInt
(
16.
W
)))
val
ibuf_pc
=
Reg
(
Vec
(
IBufSize
*
2
,
UInt
(
VAddrBits
.
W
)))
val
ibuf_pnpc
=
Reg
(
Vec
(
IBufSize
*
2
,
UInt
(
VAddrBits
.
W
)))
val
ibuf_valid
=
RegInit
(
VecInit
(
Seq
.
fill
(
IBufSize
*
2
)(
false
.
B
)))
val
head_ptr
=
RegInit
(
0.
U
(
log2Up
(
IBufSize
*
2
).
W
))
val
tail_ptr
=
RegInit
(
0.
U
(
log2Up
(
IBufSize
*
2
).
W
))
...
...
@@ -48,6 +49,7 @@ class Ibuffer extends XSModule {
when
(
io
.
in
.
bits
.
mask
(
i
))
{
ibuf
(
tail_ptr
+
enq_idx
)
:=
Mux
(
i
.
U
(
0
),
io
.
in
.
bits
.
instrs
(
i
>>
1
)(
31
,
16
),
io
.
in
.
bits
.
instrs
(
i
>>
1
)(
15
,
0
))
ibuf_pc
(
tail_ptr
+
enq_idx
)
:=
io
.
in
.
bits
.
pc
+
(
enq_idx
<<
1
).
asUInt
ibuf_pnpc
(
tail_ptr
+
enq_idx
)
:=
io
.
in
.
bits
.
pnpc
(
i
>>
1
)
ibuf_valid
(
tail_ptr
+
enq_idx
)
:=
true
.
B
}
enq_idx
=
enq_idx
+
io
.
in
.
bits
.
mask
(
i
)
...
...
@@ -66,6 +68,7 @@ class Ibuffer extends XSModule {
// is RVC
io
.
out
(
i
).
bits
.
instr
:=
Cat
(
0.
U
(
16.
W
),
ibuf
(
head_ptr
+
deq_idx
))
io
.
out
(
i
).
bits
.
pc
:=
ibuf_pc
(
head_ptr
+
deq_idx
)
io
.
out
(
i
).
bits
.
pnpc
:=
ibuf_pnpc
(
head_ptr
+
deq_idx
)
io
.
out
(
i
).
bits
.
isRVC
:=
true
.
B
io
.
out
(
i
).
valid
:=
true
.
B
ibuf_valid
(
head_ptr
+
deq_idx
)
:=
false
.
B
...
...
@@ -73,6 +76,7 @@ class Ibuffer extends XSModule {
// isn't RVC
io
.
out
(
i
).
bits
.
instr
:=
Cat
(
ibuf
(
head_ptr
+
deq_idx
+
1.
U
),
ibuf
(
head_ptr
+
deq_idx
))
io
.
out
(
i
).
bits
.
pc
:=
ibuf_pc
(
head_ptr
+
deq_idx
)
io
.
out
(
i
).
bits
.
pnpc
:=
ibuf_pnpc
(
head_ptr
+
deq_idx
)
io
.
out
(
i
).
bits
.
isRVC
:=
false
.
B
io
.
out
(
i
).
valid
:=
true
.
B
ibuf_valid
(
head_ptr
+
deq_idx
)
:=
false
.
B
...
...
@@ -81,12 +85,14 @@ class Ibuffer extends XSModule {
// half inst keep in buffer
io
.
out
(
i
).
bits
.
instr
:=
0.
U
(
32.
W
)
io
.
out
(
i
).
bits
.
pc
:=
0.
U
(
VAddrBits
.
W
)
io
.
out
(
i
).
bits
.
pnpc
:=
0.
U
(
VAddrBits
.
W
)
io
.
out
(
i
).
bits
.
isRVC
:=
false
.
B
io
.
out
(
i
).
valid
:=
false
.
B
}
}.
otherwise
{
io
.
out
(
i
).
bits
.
instr
:=
0.
U
io
.
out
(
i
).
bits
.
pc
:=
0.
U
io
.
out
(
i
).
bits
.
pnpc
:=
0.
U
io
.
out
(
i
).
bits
.
isRVC
:=
false
.
B
io
.
out
(
i
).
valid
:=
false
.
B
}
...
...
@@ -108,6 +114,7 @@ class Ibuffer extends XSModule {
for
(
i
<-
0
until
DecodeWidth
)
{
io
.
out
(
i
).
bits
.
instr
:=
0.
U
io
.
out
(
i
).
bits
.
pc
:=
0.
U
io
.
out
(
i
).
bits
.
pnpc
:=
0.
U
io
.
out
(
i
).
bits
.
isRVC
:=
false
.
B
io
.
out
(
i
).
valid
:=
false
.
B
}
...
...
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