Skip to content
体验新版
项目
组织
正在加载...
登录
切换导航
打开侧边栏
OpenXiangShan
XiangShan
提交
fb4849e5
X
XiangShan
项目概览
OpenXiangShan
/
XiangShan
10 个月 前同步成功
通知
1183
Star
3914
Fork
526
代码
文件
提交
分支
Tags
贡献者
分支图
Diff
Issue
0
列表
看板
标记
里程碑
合并请求
0
DevOps
流水线
流水线任务
计划
Wiki
0
Wiki
分析
仓库
DevOps
项目成员
Pages
X
XiangShan
项目概览
项目概览
详情
发布
仓库
仓库
文件
提交
分支
标签
贡献者
分支图
比较
Issue
0
Issue
0
列表
看板
标记
里程碑
合并请求
0
合并请求
0
Pages
DevOps
DevOps
流水线
流水线任务
计划
分析
分析
仓库分析
DevOps
Wiki
0
Wiki
成员
成员
收起侧边栏
关闭侧边栏
动态
分支图
创建新Issue
流水线任务
提交
Issue看板
前往新版Gitcode,体验更适合开发者的 AI 搜索 >>
提交
fb4849e5
编写于
6月 10, 2023
作者:
X
Xuan Hu
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
backend: refactor bundle connection
上级
25bcff47
变更
1
隐藏空白更改
内联
并排
Showing
1 changed file
with
10 addition
and
8 deletion
+10
-8
src/main/scala/xiangshan/backend/Backend.scala
src/main/scala/xiangshan/backend/Backend.scala
+10
-8
未找到文件。
src/main/scala/xiangshan/backend/Backend.scala
浏览文件 @
fb4849e5
...
...
@@ -12,7 +12,7 @@ import xiangshan.backend.datapath.WbConfig._
import
xiangshan.backend.datapath.
{
DataPath
,
NewPipelineConnect
,
WbDataPath
}
import
xiangshan.backend.exu.ExuBlock
import
xiangshan.backend.fu.vector.Bundles.
{
VConfig
,
VType
}
import
xiangshan.backend.fu.
{
FenceIO
,
FenceToSbuffer
,
PerfCounterIO
,
FuConfig
}
import
xiangshan.backend.fu.
{
FenceIO
,
FenceToSbuffer
,
FuConfig
,
PerfCounterIO
}
import
xiangshan.backend.issue.
{
Scheduler
,
IntScheduler
,
MemScheduler
,
VfScheduler
}
import
xiangshan.backend.rob.RobLsqIO
import
xiangshan.frontend.
{
FtqPtr
,
FtqRead
}
...
...
@@ -292,6 +292,8 @@ class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends
}
}
private
val
vconfig
=
dataPath
.
io
.
vconfigReadPort
.
data
ctrlBlock
.
io
.
fromTop
.
hartId
:=
io
.
fromTop
.
hartId
ctrlBlock
.
io
.
frontend
<>
io
.
frontend
ctrlBlock
.
io
.
fromWB
.
wbData
<>
wbDataPath
.
io
.
toCtrlBlock
.
writeback
...
...
@@ -303,6 +305,7 @@ class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends
ctrlBlock
.
io
.
robio
.
csr
.
isXRet
:=
intExuBlock
.
io
.
csrio
.
get
.
isXRet
ctrlBlock
.
io
.
robio
.
csr
.
wfiEvent
:=
intExuBlock
.
io
.
csrio
.
get
.
wfi_event
ctrlBlock
.
io
.
robio
.
lsq
<>
io
.
mem
.
robLsqIO
ctrlBlock
.
io
.
fromDataPath
.
vtype
:=
vconfig
(
7
,
0
).
asTypeOf
(
new
VType
)
intScheduler
.
io
.
fromTop
.
hartId
:=
io
.
fromTop
.
hartId
intScheduler
.
io
.
fromCtrlBlock
.
flush
:=
ctrlBlock
.
io
.
toIssueBlock
.
flush
...
...
@@ -312,6 +315,7 @@ class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends
intScheduler
.
io
.
fromDispatch
.
uops
<>
ctrlBlock
.
io
.
toIssueBlock
.
intUops
intScheduler
.
io
.
intWriteBack
:=
wbDataPath
.
io
.
toIntPreg
intScheduler
.
io
.
vfWriteBack
:=
0.
U
.
asTypeOf
(
intScheduler
.
io
.
vfWriteBack
)
intScheduler
.
io
.
fromDataPath
:=
dataPath
.
io
.
toIntIQ
memScheduler
.
io
.
fromTop
.
hartId
:=
io
.
fromTop
.
hartId
memScheduler
.
io
.
fromCtrlBlock
.
flush
:=
ctrlBlock
.
io
.
toIssueBlock
.
flush
...
...
@@ -329,8 +333,9 @@ class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends
sink
.
bits
.
uop
:=
0.
U
.
asTypeOf
(
sink
.
bits
.
uop
)
sink
.
bits
.
uop
.
robIdx
:=
source
.
bits
.
robIdx
}
io
.
mem
.
ldaIqFeedback
<>
memScheduler
.
io
.
fromMem
.
get
.
ldaFeedback
io
.
mem
.
staIqFeedback
<>
memScheduler
.
io
.
fromMem
.
get
.
staFeedback
memScheduler
.
io
.
fromDataPath
:=
dataPath
.
io
.
toMemIQ
memScheduler
.
io
.
fromMem
.
get
.
ldaFeedback
:=
io
.
mem
.
ldaIqFeedback
memScheduler
.
io
.
fromMem
.
get
.
staFeedback
:=
io
.
mem
.
staIqFeedback
vfScheduler
.
io
.
fromTop
.
hartId
:=
io
.
fromTop
.
hartId
vfScheduler
.
io
.
fromCtrlBlock
.
flush
:=
ctrlBlock
.
io
.
toIssueBlock
.
flush
...
...
@@ -338,16 +343,15 @@ class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends
vfScheduler
.
io
.
fromDispatch
.
uops
<>
ctrlBlock
.
io
.
toIssueBlock
.
vfUops
vfScheduler
.
io
.
intWriteBack
:=
0.
U
.
asTypeOf
(
vfScheduler
.
io
.
intWriteBack
)
vfScheduler
.
io
.
vfWriteBack
:=
wbDataPath
.
io
.
toVfPreg
vfScheduler
.
io
.
fromDataPath
:=
dataPath
.
io
.
toVfIQ
dataPath
.
io
.
flush
:=
ctrlBlock
.
io
.
toDataPath
.
flush
dataPath
.
io
.
vconfigReadPort
.
addr
:=
ctrlBlock
.
io
.
toDataPath
.
vtypeAddr
val
vconfig
=
dataPath
.
io
.
vconfigReadPort
.
data
ctrlBlock
.
io
.
fromDataPath
.
vtype
:=
vconfig
(
7
,
0
).
asTypeOf
(
new
VType
)
for
(
i
<-
0
until
dataPath
.
io
.
fromIntIQ
.
length
)
{
for
(
j
<-
0
until
dataPath
.
io
.
fromIntIQ
(
i
).
length
)
{
NewPipelineConnect
(
intScheduler
.
io
.
toDataPath
(
i
)(
j
),
dataPath
.
io
.
fromIntIQ
(
i
)(
j
),
dataPath
.
io
.
fromIntIQ
(
i
)(
j
).
valid
,
intScheduler
.
io
.
toDataPath
(
i
)(
j
).
bits
.
common
.
robIdx
.
needFlush
(
ctrlBlock
.
io
.
toDataPath
.
flush
),
Option
(
"intScheduler2DataPathPipe"
))
intScheduler
.
io
.
fromDataPath
(
i
)(
j
)
:=
dataPath
.
io
.
toIntIQ
(
i
)(
j
)
}
}
...
...
@@ -355,7 +359,6 @@ class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends
for
(
j
<-
0
until
dataPath
.
io
.
fromVfIQ
(
i
).
length
)
{
NewPipelineConnect
(
vfScheduler
.
io
.
toDataPath
(
i
)(
j
),
dataPath
.
io
.
fromVfIQ
(
i
)(
j
),
dataPath
.
io
.
fromVfIQ
(
i
)(
j
).
valid
,
vfScheduler
.
io
.
toDataPath
(
i
)(
j
).
bits
.
common
.
robIdx
.
needFlush
(
ctrlBlock
.
io
.
toDataPath
.
flush
),
Option
(
"vfScheduler2DataPathPipe"
))
vfScheduler
.
io
.
fromDataPath
(
i
)(
j
)
:=
dataPath
.
io
.
toVfIQ
(
i
)(
j
)
}
}
...
...
@@ -363,7 +366,6 @@ class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends
for
(
j
<-
0
until
dataPath
.
io
.
fromMemIQ
(
i
).
length
)
{
NewPipelineConnect
(
memScheduler
.
io
.
toDataPath
(
i
)(
j
),
dataPath
.
io
.
fromMemIQ
(
i
)(
j
),
dataPath
.
io
.
fromMemIQ
(
i
)(
j
).
valid
,
memScheduler
.
io
.
toDataPath
(
i
)(
j
).
bits
.
common
.
robIdx
.
needFlush
(
ctrlBlock
.
io
.
toDataPath
.
flush
),
Option
(
"memScheduler2DataPathPipe"
))
memScheduler
.
io
.
fromDataPath
(
i
)(
j
)
:=
dataPath
.
io
.
toMemIQ
(
i
)(
j
)
}
}
...
...
编辑
预览
Markdown
is supported
0%
请重试
或
添加新附件
.
添加附件
取消
You are about to add
0
people
to the discussion. Proceed with caution.
先完成此消息的编辑!
取消
想要评论请
注册
或
登录