split jbtac into independent file

src/main/scala/xiangshan/frontend/BPU.scala

@@ -111,40 +111,24 @@ class BPUStage1 extends XSModule {
   val btbTargets = VecInit(btb.io.out.dEntries.map(_.target))
   val btbTypes = VecInit(btb.io.out.dEntries.map(_._type))
 
-  // JBTAC, divided into 8 banks, makes prediction for indirect jump except ret.
-  val jbtacAddr = new TableAddr(log2Up(JbtacSize), JbtacBanks)
-  def jbtacEntry() = new Bundle {
-    val valid = Bool()
-    // TODO: don't need full length of tag and target
-    val tag = UInt(jbtacAddr.tagBits.W)
-    val target = UInt(VAddrBits.W)
-    val offset = UInt(log2Up(FetchWidth).W)
-  }
 
-  val jbtac = List.fill(JbtacBanks)(Module(new SRAMTemplate(jbtacEntry(), set = JbtacSize / JbtacBanks, shouldReset = true, holdRead = true, singlePort = false)))
-
-  val jbtacRead = Wire(Vec(JbtacBanks, jbtacEntry()))
-
-  val jbtacFire = Reg(Vec(JbtacBanks, Bool()))
-  // Only read one bank
-  val histXORAddr = io.in.pc.bits ^ Cat(hist, 0.U(2.W))(VAddrBits - 1, 0)
-  val histXORAddrLatch = RegEnable(histXORAddr, io.in.pc.valid)
-  jbtacFire := 0.U.asTypeOf(Vec(JbtacBanks, Bool()))
-  (0 until JbtacBanks).map(
-    b => {
-      jbtac(b).reset := reset.asBool
-      jbtac(b).io.r.req.valid := io.in.pc.fire() && b.U === jbtacAddr.getBank(histXORAddr)
-      jbtac(b).io.r.req.bits.setIdx := jbtacAddr.getBankIdx(histXORAddr)
-      jbtacFire(b) := jbtac(b).io.r.req.fire()
-      jbtacRead(b) := jbtac(b).io.r.resp.data(0)
-    }
-  )
+  val jbtac = Module(new JBTAC)
+  jbtac.io.in.pc <> io.in.pc
+  jbtac.io.in.pcLatch := pcLatch
+  jbtac.io.in.hist := hist
+  jbtac.io.redirectValid := io.redirectInfo.valid
+  jbtac.io.flush := io.flush
+
+  jbtac.io.update.fetchPC := updateFetchpc
+  jbtac.io.update.fetchIdx := r.fetchIdx
+  jbtac.io.update.misPred := io.redirectInfo.misPred
+  jbtac.io.update._type := r._type
+  jbtac.io.update.target := r.target
+  jbtac.io.update.hist := r.hist
 
-  val jbtacBank = jbtacAddr.getBank(histXORAddrLatch)
-  // val jbtacHit = jbtacRead(jbtacBank).valid && jbtacRead(jbtacBank).tag === jbtacAddr.getTag(pcLatch) && !flushS1 && jbtacFire(jbtacBank)
-  val jbtacHit = jbtacRead(jbtacBank).valid && jbtacRead(jbtacBank).tag === jbtacAddr.getTag(pcLatch) && !io.flush && jbtacFire(jbtacBank)
-  val jbtacHitIdx = jbtacRead(jbtacBank).offset
-  val jbtacTarget = jbtacRead(jbtacBank).target
+  val jbtacHit = jbtac.io.out.hit
+  val jbtacTarget = jbtac.io.out.target
+  val jbtacHitIdx = jbtac.io.out.hitIdx
 
   // calculate global history of each instr
   val firstHist = RegNext(hist)
@@ -160,32 +144,7 @@ class BPUStage1 extends XSModule {
   }
   (0 until FetchWidth).map(i => io.s1OutPred.bits.hist(i) := firstHist << histShift(i))
 
-  // update btb, jbtac, ghr
-
-
-  // 2. update jbtac
-  val jbtacWrite = Wire(jbtacEntry())
-  // val updateHistXORAddr = updateFetchpc ^ Cat(r.hist, 0.U(2.W))(VAddrBits - 1, 0)
-  val updateHistXORAddr = updateFetchpc ^ Cat(r.hist, 0.U(2.W))(VAddrBits - 1, 0)
-  jbtacWrite.valid := true.B
-  // jbtacWrite.tag := jbtacAddr.getTag(updateFetchpc)
-  jbtacWrite.tag := jbtacAddr.getTag(updateFetchpc)
-  jbtacWrite.target := r.target
-  // jbtacWrite.offset := updateFetchIdx
-  jbtacWrite.offset := r.fetchIdx
-  for (b <- 0 until JbtacBanks) {
-    when (b.U === jbtacAddr.getBank(updateHistXORAddr)) {
-      jbtac(b).io.w.req.valid := io.redirectInfo.valid && io.redirectInfo.misPred && r._type === BTBtype.I
-      jbtac(b).io.w.req.bits.setIdx := jbtacAddr.getBankIdx(updateHistXORAddr)
-      jbtac(b).io.w.req.bits.data := jbtacWrite
-    }.otherwise {
-      jbtac(b).io.w.req.valid := false.B
-      jbtac(b).io.w.req.bits.setIdx := DontCare
-      jbtac(b).io.w.req.bits.data := DontCare
-    }
-  }
-
-  // 3. update ghr
+  // update ghr
   updateGhr := io.s1OutPred.bits.redirect || io.flush
   val brJumpIdx = Mux(!(btbHit && btbTaken), 0.U, UIntToOH(btbTakenIdx))
   val indirectIdx = Mux(!jbtacHit, 0.U, UIntToOH(jbtacHitIdx))

src/main/scala/xiangshan/frontend/btb.scala

@@ -26,15 +26,8 @@ class BTBPred extends XSBundle {
   val target = UInt(VAddrBits.W)
 
   val writeWay = UInt(log2Up(BtbWays).W)
-  // val ctrs = Vec(FetchWidth, UInt(2.W))
   val notTakens = Vec(FetchWidth, Bool())
-  // val valids = Vec(FetchWidth, Bool())
   val dEntries = Vec(FetchWidth, btbDataEntry())
-
-  // val toS2 = new Bundle{
-    // val hits = UInt(FetchWidth.W)
-    // val targets = Vec(FetchWidth, UInt(VAddrBits.W))
-  // }
 }
 
 case class btbDataEntry() extends XSBundle {
@@ -69,9 +62,6 @@ class BTB extends XSModule {
 
   val btbAddr = new TableAddr(log2Up(BtbSets), BtbBanks)
 
-  // val predictWidth = FetchWidth
-
-
   // SRAMs to store BTB meta & data
   val btbMeta = List.fill(BtbWays)(List.fill(BtbBanks)(
     Module(new SRAMTemplate(btbMetaEntry(), set = BtbSets / BtbBanks, way = 1, shouldReset = true, holdRead = true))
@@ -129,15 +119,11 @@ class BTB extends XSModule {
   dataEntries.map(_.pred := DontCare)
   dataEntries.map(_.target := DontCare)
   dataEntries.map(_._type := DontCare)
-  // btbTargets := DontCare
-  // btbCtrs := DontCare
-  // btbTakens := DontCare
-  // btbTypes := DontCare
+
 
   for (w <- 0 until BtbWays) {
     for (b <- 0 until BtbBanks) { readFire(w)(b) := btbMeta(w)(b).io.r.req.fire() && btbData(w)(b).io.r.req.fire() }
     when (metaRead(w).valid && metaRead(w).tag === btbAddr.getTag(pcLatch)) {
-      // btbWayHits(w) := !flushS1 && RegNext(btbReadFire(w)(btbHitBank), init = false.B)
       wayHits(w) := !io.flush && RegNext(readFire(w)(readBankIdx), init = false.B)
       for (i <- 0 until FetchWidth) {
         dataEntries(i).valid := dataRead(w)(i).valid
@@ -193,7 +179,6 @@ class BTB extends XSModule {
   btbDataWrite.target := u.target
   btbDataWrite.pred := newCtr
   btbDataWrite._type := u._type
-  // btbDataWrite.offset := DontCare
 
   val isBr = u._type === BTBtype.B
   val isJ = u._type === BTBtype.J
@@ -233,10 +218,6 @@ class BTB extends XSModule {
   io.out.takenIdx := takenIdx
   io.out.target := takenTarget
   io.out.writeWay := writeWay
-  // io.out.ctrs := VecInit(dataEntries.map(_.pred))
   io.out.notTakens := notTakenBranches
   io.out.dEntries := dataEntries
-  // io.out.valids := VecInit(dataEntries.map(_.valid))
-  // io.toS2.hits := Cat(dataEntries.map(_.valid))
-  // io.toS2.targets := VecInit(dataEntries.map(_.target))
 }
\ No newline at end of file

src/main/scala/xiangshan/frontend/jbtac.scala

+package xiangshan.frontend
+
+import chisel3._
+import chisel3.util._
+import xiangshan._
+import xiangshan.utils._
+import xiangshan.backend.ALUOpType
+import utils._
+
+
+class JBTACUpdateBundle extends XSBundle {
+  val fetchPC = UInt(VAddrBits.W)
+  val fetchIdx = UInt(log2Up(FetchWidth).W)
+  val hist = UInt(HistoryLength.W)
+  val target = UInt(VAddrBits.W)
+  val _type = UInt(2.W)
+  val misPred = Bool()
+}
+
+class JBTACPred extends XSBundle {
+  val hit = Bool()
+  val target = UInt(VAddrBits.W)
+  val hitIdx = UInt(log2Up(FetchWidth).W)
+}
+
+class JBTAC extends XSModule {
+  val io = IO(new Bundle {
+    val in = new Bundle {
+      val pc = Flipped(Decoupled(UInt(VAddrBits.W)))
+      val pcLatch = Input(UInt(VAddrBits.W))
+      val hist = Input(UInt(HistoryLength.W))
+    }
+    val redirectValid = Input(Bool())
+    val flush = Input(Bool())
+    val update = Input(new JBTACUpdateBundle)
+
+    val out = Output(new JBTACPred)
+  })
+
+  io.in.pc.ready := true.B
+  // JBTAC, divided into 8 banks, makes prediction for indirect jump except ret.
+  val jbtacAddr = new TableAddr(log2Up(JbtacSize), JbtacBanks)
+  def jbtacEntry() = new Bundle {
+    val valid = Bool()
+    // TODO: don't need full length of tag and target
+    val tag = UInt(jbtacAddr.tagBits.W)
+    val target = UInt(VAddrBits.W)
+    val offset = UInt(log2Up(FetchWidth).W)
+  }
+
+  val jbtac = List.fill(JbtacBanks)(Module(new SRAMTemplate(jbtacEntry(), set = JbtacSize / JbtacBanks, shouldReset = true, holdRead = true, singlePort = false)))
+
+  val readEntries = Wire(Vec(JbtacBanks, jbtacEntry()))
+
+  val readFire = Reg(Vec(JbtacBanks, Bool()))
+  // Only read one bank
+  val histXORAddr = io.in.pc.bits ^ Cat(io.in.hist, 0.U(2.W))(VAddrBits - 1, 0)
+  val histXORAddrLatch = RegEnable(histXORAddr, io.in.pc.valid)
+  readFire := 0.U.asTypeOf(Vec(JbtacBanks, Bool()))
+  (0 until JbtacBanks).map(
+    b => {
+      jbtac(b).reset := reset.asBool
+      jbtac(b).io.r.req.valid := io.in.pc.fire() && b.U === jbtacAddr.getBank(histXORAddr)
+      jbtac(b).io.r.req.bits.setIdx := jbtacAddr.getBankIdx(histXORAddr)
+      readFire(b) := jbtac(b).io.r.req.fire()
+      readEntries(b) := jbtac(b).io.r.resp.data(0)
+    }
+  )
+
+  val bank = jbtacAddr.getBank(histXORAddrLatch)
+
+  io.out.hit := readEntries(bank).valid && readEntries(bank).tag === jbtacAddr.getTag(io.in.pcLatch) && !io.flush && readFire(bank)
+  io.out.hitIdx := readEntries(bank).offset
+  io.out.target := readEntries(bank).target
+
+    // 2. update jbtac
+  val writeEntry = Wire(jbtacEntry())
+  // val updateHistXORAddr = updatefetchPC ^ Cat(r.hist, 0.U(2.W))(VAddrBits - 1, 0)
+  val updateHistXORAddr = io.update.fetchPC ^ Cat(io.update.hist, 0.U(2.W))(VAddrBits - 1, 0)
+  writeEntry.valid := true.B
+  // writeEntry.tag := jbtacAddr.getTag(updatefetchPC)
+  writeEntry.tag := jbtacAddr.getTag(io.update.fetchPC)
+  writeEntry.target := io.update.target
+  // writeEntry.offset := updateFetchIdx
+  writeEntry.offset := io.update.fetchIdx
+  for (b <- 0 until JbtacBanks) {
+    when (b.U === jbtacAddr.getBank(updateHistXORAddr)) {
+      jbtac(b).io.w.req.valid := io.redirectValid && io.update.misPred && io.update._type === BTBtype.I
+      jbtac(b).io.w.req.bits.setIdx := jbtacAddr.getBankIdx(updateHistXORAddr)
+      jbtac(b).io.w.req.bits.data := writeEntry
+    }.otherwise {
+      jbtac(b).io.w.req.valid := false.B
+      jbtac(b).io.w.req.bits.setIdx := DontCare
+      jbtac(b).io.w.req.bits.data := DontCare
+    }
+  }
+}
\ No newline at end of file