Merge pull request #401 from RISCVERS/putDCacheAndUnCacheIntoMemBlock

put dcache and uncache into MemBlock

src/main/scala/system/SoC.scala

@@ -97,10 +97,10 @@ class XSSoc()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
   // connections
   // -------------------------------------------------
   for (i <- 0 until NumCores) {
-    l2_xbar(i) := TLBuffer() := DebugIdentityNode() := xs_core(i).dcache.clientNode
+    l2_xbar(i) := TLBuffer() := DebugIdentityNode() := xs_core(i).memBlock.dcache.clientNode
     l2_xbar(i) := TLBuffer() := DebugIdentityNode() := xs_core(i).l1pluscache.clientNode
     l2_xbar(i) := TLBuffer() := DebugIdentityNode() := xs_core(i).ptw.node
-    mmioXbar   := TLBuffer() := DebugIdentityNode() := xs_core(i).uncache.clientNode
+    mmioXbar   := TLBuffer() := DebugIdentityNode() := xs_core(i).memBlock.uncache.clientNode
     l2cache(i).node := TLBuffer() := DebugIdentityNode() := l2_xbar(i)
     l3_xbar := TLBuffer() := DebugIdentityNode() := l2cache(i).node
   }

src/main/scala/xiangshan/XSCore.scala

@@ -261,13 +261,33 @@ object AddressSpace extends HasXSParameter {
 
 
 
-class XSCore()(implicit p: config.Parameters) extends LazyModule with HasXSParameter {
+class XSCore()(implicit p: config.Parameters) extends LazyModule
+  with HasXSParameter
+  with HasExeBlockHelper
+{
+
+  // to fast wake up fp, mem rs
+  val intBlockFastWakeUpFp = intExuConfigs.filter(fpFastFilter)
+  val intBlockSlowWakeUpFp = intExuConfigs.filter(fpSlowFilter)
+  val intBlockFastWakeUpInt = intExuConfigs.filter(intFastFilter)
+  val intBlockSlowWakeUpInt = intExuConfigs.filter(intSlowFilter)
+
+  val fpBlockFastWakeUpFp = fpExuConfigs.filter(fpFastFilter)
+  val fpBlockSlowWakeUpFp = fpExuConfigs.filter(fpSlowFilter)
+  val fpBlockFastWakeUpInt = fpExuConfigs.filter(intFastFilter)
+  val fpBlockSlowWakeUpInt = fpExuConfigs.filter(intSlowFilter)
 
   // outer facing nodes
-  val dcache = LazyModule(new DCache())
-  val uncache = LazyModule(new Uncache())
   val l1pluscache = LazyModule(new L1plusCache())
   val ptw = LazyModule(new PTW())
+  val memBlock = LazyModule(new MemBlock(
+    fastWakeUpIn = intBlockFastWakeUpInt ++ intBlockFastWakeUpFp ++ fpBlockFastWakeUpInt ++ fpBlockFastWakeUpFp,
+    slowWakeUpIn = intBlockSlowWakeUpInt ++ intBlockSlowWakeUpFp ++ fpBlockSlowWakeUpInt ++ fpBlockSlowWakeUpFp,
+    fastFpOut = Seq(),
+    slowFpOut = loadExuConfigs,
+    fastIntOut = Seq(),
+    slowIntOut = loadExuConfigs
+  ))
 
   lazy val module = new XSCoreImp(this)
 }
@@ -311,20 +331,10 @@ class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
     fastIntOut = fpBlockFastWakeUpInt,
     slowIntOut = fpBlockSlowWakeUpInt
   ))
-  val memBlock = Module(new MemBlock(
-    fastWakeUpIn = intBlockFastWakeUpInt ++ intBlockFastWakeUpFp ++ fpBlockFastWakeUpInt ++ fpBlockFastWakeUpFp,
-    slowWakeUpIn = intBlockSlowWakeUpInt ++ intBlockSlowWakeUpFp ++ fpBlockSlowWakeUpInt ++ fpBlockSlowWakeUpFp,
-    fastFpOut = Seq(),
-    slowFpOut = loadExuConfigs,
-    fastIntOut = Seq(),
-    slowIntOut = loadExuConfigs
-  ))
 
-  val dcache = outer.dcache.module
-  val uncache = outer.uncache.module
+  val memBlock = outer.memBlock.module
   val l1pluscache = outer.l1pluscache.module
   val ptw = outer.ptw.module
-  
 
   frontend.io.backend <> ctrlBlock.io.frontend
   frontend.io.sfence <> integerBlock.io.fenceio.sfence
@@ -399,9 +409,6 @@ class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
   ptw.io.sfence <> integerBlock.io.fenceio.sfence
   ptw.io.csr    <> integerBlock.io.csrio.tlb
 
-  dcache.io.lsu  <> memBlock.io.dcache
-  uncache.io.lsq <> memBlock.io.uncache
-
   if (!env.FPGAPlatform) {
     val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W))))
     ExcitingUtils.addSink(debugIntReg, "DEBUG_INT_ARCH_REG", ExcitingUtils.Debug)

src/main/scala/xiangshan/backend/MemBlock.scala

@@ -2,13 +2,16 @@ package xiangshan.backend
 
 import chisel3._
 import chisel3.util._
+import chipsalliance.rocketchip.config.Parameters
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
+import freechips.rocketchip.tile.HasFPUParameters
 import xiangshan._
 import xiangshan.backend.exu.Exu.{loadExuConfigs, storeExuConfigs}
 import xiangshan.backend.roq.RoqPtr
 import xiangshan.backend.exu._
 import xiangshan.cache._
 import xiangshan.mem._
-import xiangshan.backend.fu.FenceToSbuffer
+import xiangshan.backend.fu.{HasExceptionNO, FenceToSbuffer}
 import xiangshan.backend.issue.{ReservationStationCtrl, ReservationStationData}
 import xiangshan.backend.regfile.RfReadPort
 
@@ -26,7 +29,22 @@ class FpBlockToMemBlockIO extends XSBundle {
   val readFpRf = Vec(exuParameters.StuCnt, new RfReadPort(XLEN + 1))
 }
 
-class MemBlock
+class MemBlock(
+  fastWakeUpIn: Seq[ExuConfig],
+  slowWakeUpIn: Seq[ExuConfig],
+  fastFpOut: Seq[ExuConfig],
+  slowFpOut: Seq[ExuConfig],
+  fastIntOut: Seq[ExuConfig],
+  slowIntOut: Seq[ExuConfig]
+)(implicit p: Parameters) extends LazyModule {
+
+  val dcache = LazyModule(new DCache())
+  val uncache = LazyModule(new Uncache())
+
+  lazy val module = new MemBlockImp(fastWakeUpIn, slowWakeUpIn, fastFpOut, slowFpOut, fastIntOut, slowIntOut)(this)
+}
+
+class MemBlockImp
 (
   fastWakeUpIn: Seq[ExuConfig],
   slowWakeUpIn: Seq[ExuConfig],
@@ -34,7 +52,13 @@ class MemBlock
   slowFpOut: Seq[ExuConfig],
   fastIntOut: Seq[ExuConfig],
   slowIntOut: Seq[ExuConfig]
-) extends XSModule with HasExeBlockHelper {
+) (outer: MemBlock) extends LazyModuleImp(outer)
+  with HasXSParameter
+  with HasExceptionNO
+  with HasXSLog
+  with HasFPUParameters
+  with HasExeBlockHelper
+{
 
   val io = IO(new Bundle {
     val fromCtrlBlock = Flipped(new CtrlToLsBlockIO)
@@ -47,9 +71,6 @@ class MemBlock
     val wakeUpIntOut = Flipped(new WakeUpBundle(fastIntOut.size, slowIntOut.size))
 
     val ptw = new TlbPtwIO
-    // TODO: dcache should be inside MemBlock
-    val dcache = Flipped(new DCacheToLsuIO)
-    val uncache = new DCacheWordIO
     val sfence = Input(new SfenceBundle)
     val tlbCsr = Input(new TlbCsrBundle)
     val fenceToSbuffer = Flipped(new FenceToSbuffer)
@@ -61,6 +82,9 @@ class MemBlock
     }
   })
 
+  val dcache = outer.dcache.module
+  val uncache = outer.uncache.module
+
   val redirect = io.fromCtrlBlock.redirect
 
   val loadUnits = Seq.fill(exuParameters.LduCnt)(Module(new LoadUnit))
@@ -113,10 +137,10 @@ class MemBlock
     val rsCtrl = Module(new ReservationStationCtrl(cfg, wakeupCnt, extraListenPortsCnt, fixedDelay = certainLatency, feedback = feedback))
     val rsData = Module(new ReservationStationData(cfg, wakeupCnt, extraListenPortsCnt, fixedDelay = certainLatency, feedback = feedback))
 
-    rsCtrl.io.data <> rsData.io.ctrl
+    rsCtrl.io.data     <> rsData.io.ctrl
     rsCtrl.io.redirect <> redirect // TODO: remove it
     rsCtrl.io.numExist <> io.toCtrlBlock.numExist(i)
-    rsCtrl.io.enqCtrl <> io.fromCtrlBlock.enqIqCtrl(i)
+    rsCtrl.io.enqCtrl  <> io.fromCtrlBlock.enqIqCtrl(i)
 
     val src2IsFp = RegNext(io.fromCtrlBlock.enqIqCtrl(i).bits.ctrl.src2Type === SrcType.fp)
     rsData.io.srcRegValue := DontCare
@@ -129,7 +153,7 @@ class MemBlock
     rsData.io.writeBackedData <> writeBackData
     for ((x, y) <- rsData.io.extraListenPorts.zip(extraListenPorts)) {
       x.valid := y.fire()
-      x.bits := y.bits
+      x.bits  := y.bits
     }
 
     // exeUnits(i).io.redirect <> redirect
@@ -152,23 +176,23 @@ class MemBlock
   io.wakeUpIn.fast.foreach(_.ready := true.B)
   io.wakeUpIn.slow.foreach(_.ready := true.B)
 
-  io.wakeUpFpOut.slow <> fpExeWbReqs
+  io.wakeUpFpOut.slow  <> fpExeWbReqs
   io.wakeUpIntOut.slow <> intExeWbReqs
 
   // load always ready
   fpExeWbReqs.foreach(_.ready := true.B)
   intExeWbReqs.foreach(_.ready := true.B)
 
-  val dtlb = Module(new TLB(Width = DTLBWidth, isDtlb = true))
-  val lsq = Module(new LsqWrappper)
+  val dtlb    = Module(new TLB(Width = DTLBWidth, isDtlb = true))
+  val lsq     = Module(new LsqWrappper)
   val sbuffer = Module(new NewSbuffer)
   // if you wants to stress test dcache store, use FakeSbuffer
   // val sbuffer = Module(new FakeSbuffer)
 
   // dtlb
-  io.ptw <> dtlb.io.ptw
+  io.ptw         <> dtlb.io.ptw
   dtlb.io.sfence <> io.sfence
-  dtlb.io.csr <> io.tlbCsr
+  dtlb.io.csr    <> io.tlbCsr
 
   // LoadUnit
   for (i <- 0 until exuParameters.LduCnt) {
@@ -178,7 +202,7 @@ class MemBlock
     // get input form dispatch
     loadUnits(i).io.ldin          <> reservationStations(i).io.deq
     // dcache access
-    loadUnits(i).io.dcache        <> io.dcache.load(i)
+    loadUnits(i).io.dcache        <> dcache.io.lsu.load(i)
     // forward
     loadUnits(i).io.lsq.forward   <> lsq.io.forward(i)
     loadUnits(i).io.sbuffer       <> sbuffer.io.forward(i)
@@ -190,46 +214,43 @@ class MemBlock
 
   // StoreUnit
   for (i <- 0 until exuParameters.StuCnt) {
-	val stu = storeUnits(i)
-	val rs = reservationStations(exuParameters.LduCnt + i)
-	val dtlbReq = dtlb.io.requestor(exuParameters.LduCnt + i)
-
-	stu.io.redirect <> io.fromCtrlBlock.redirect
-	stu.io.tlbFeedback <> rs.io.feedback
-	stu.io.dtlb <> dtlbReq
-
-	// get input from dispatch
-	stu.io.stin <> rs.io.deq
-
-	// passdown to lsq
-	stu.io.lsq <> lsq.io.storeIn(i)
-	io.toCtrlBlock.stOut(i).valid := stu.io.stout.valid
-	io.toCtrlBlock.stOut(i).bits := stu.io.stout.bits
-	stu.io.stout.ready := true.B
+    val stu = storeUnits(i)
+    val rs = reservationStations(exuParameters.LduCnt + i)
+    val dtlbReq = dtlb.io.requestor(exuParameters.LduCnt + i)
+
+    stu.io.redirect    <> io.fromCtrlBlock.redirect
+    stu.io.tlbFeedback <> rs.io.feedback
+    stu.io.dtlb        <> dtlbReq
+    stu.io.stin        <> rs.io.deq
+    stu.io.lsq         <> lsq.io.storeIn(i)
+
+    io.toCtrlBlock.stOut(i).valid := stu.io.stout.valid
+    io.toCtrlBlock.stOut(i).bits  := stu.io.stout.bits
+    stu.io.stout.ready := true.B
   }
 
   // mmio store writeback will use store writeback port 0
   lsq.io.mmioStout.ready := false.B
-  when(lsq.io.mmioStout.valid && !storeUnits(0).io.stout.valid) {
+  when (lsq.io.mmioStout.valid && !storeUnits(0).io.stout.valid) {
     io.toCtrlBlock.stOut(0).valid := true.B
     lsq.io.mmioStout.ready := true.B
     io.toCtrlBlock.stOut(0).bits  := lsq.io.mmioStout.bits
   }
 
   // Lsq
-  lsq.io.commits     <> io.lsqio.commits
-  lsq.io.enq         <> io.fromCtrlBlock.enqLsq
-  lsq.io.brqRedirect := io.fromCtrlBlock.redirect
-  lsq.io.roqDeqPtr   := io.lsqio.roqDeqPtr
+  lsq.io.commits        <> io.lsqio.commits
+  lsq.io.enq            <> io.fromCtrlBlock.enqLsq
+  lsq.io.brqRedirect    <> io.fromCtrlBlock.redirect
+  lsq.io.roqDeqPtr      <> io.lsqio.roqDeqPtr
   io.toCtrlBlock.replay <> lsq.io.rollback
-  lsq.io.dcache      <> io.dcache.lsq
-  lsq.io.uncache     <> io.uncache
+  lsq.io.dcache         <> dcache.io.lsu.lsq
+  lsq.io.uncache        <> uncache.io.lsq
 
   // LSQ to store buffer
-  lsq.io.sbuffer     <> sbuffer.io.in
+  lsq.io.sbuffer        <> sbuffer.io.in
 
   // Sbuffer
-  sbuffer.io.dcache    <> io.dcache.store
+  sbuffer.io.dcache     <> dcache.io.lsu.store
 
   // flush sbuffer
   val fenceFlush = io.fenceToSbuffer.flushSb
@@ -245,8 +266,8 @@ class MemBlock
   val s_normal :: s_atomics_0 :: s_atomics_1 :: Nil = Enum(3)
   val state = RegInit(s_normal)
 
-  val atomic_rs0 = exuParameters.LduCnt + 0
-  val atomic_rs1 = exuParameters.LduCnt + 1
+  val atomic_rs0  = exuParameters.LduCnt + 0
+  val atomic_rs1  = exuParameters.LduCnt + 1
   val st0_atomics = reservationStations(atomic_rs0).io.deq.valid && reservationStations(atomic_rs0).io.deq.bits.uop.ctrl.fuType === FuType.mou
   val st1_atomics = reservationStations(atomic_rs1).io.deq.valid && reservationStations(atomic_rs1).io.deq.bits.uop.ctrl.fuType === FuType.mou
 
@@ -275,9 +296,9 @@ class MemBlock
 
   atomicsUnit.io.dtlb.resp.valid := false.B
   atomicsUnit.io.dtlb.resp.bits  := DontCare
-  atomicsUnit.io.dtlb.req.ready := dtlb.io.requestor(0).req.ready
+  atomicsUnit.io.dtlb.req.ready  := dtlb.io.requestor(0).req.ready
 
-  atomicsUnit.io.dcache        <> io.dcache.atomics
+  atomicsUnit.io.dcache <> dcache.io.lsu.atomics
   atomicsUnit.io.flush_sbuffer.empty := sbuffer.io.flush.empty
 
   // for atomicsUnit, it uses loadUnit(0)'s TLB port
@@ -303,8 +324,7 @@ class MemBlock
     assert(!storeUnits(1).io.tlbFeedback.valid)
   }
 
-  lsq.io.exceptionAddr.lsIdx := io.lsqio.exceptionAddr.lsIdx
+  lsq.io.exceptionAddr.lsIdx  := io.lsqio.exceptionAddr.lsIdx
   lsq.io.exceptionAddr.isStore := io.lsqio.exceptionAddr.isStore
   io.lsqio.exceptionAddr.vaddr := Mux(atomicsUnit.io.exceptionAddr.valid, atomicsUnit.io.exceptionAddr.bits, lsq.io.exceptionAddr.vaddr)
-
 }