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f66e611a
编写于
7月 26, 2020
作者:
L
LinJiawei
浏览文件
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差异文件
Revert "Mem: connect mem pipeline into backend"
This reverts commit
3fedfe35
.
上级
c7dd54af
变更
4
隐藏空白更改
内联
并排
Showing
4 changed file
with
8 addition
and
39 deletion
+8
-39
src/main/scala/xiangshan/backend/Backend.scala
src/main/scala/xiangshan/backend/Backend.scala
+5
-5
src/main/scala/xiangshan/backend/exu/Exu.scala
src/main/scala/xiangshan/backend/exu/Exu.scala
+3
-3
src/main/scala/xiangshan/backend/exu/LsExeUnit.scala
src/main/scala/xiangshan/backend/exu/LsExeUnit.scala
+0
-30
src/main/scala/xiangshan/backend/package.scala
src/main/scala/xiangshan/backend/package.scala
+0
-1
未找到文件。
src/main/scala/xiangshan/backend/Backend.scala
浏览文件 @
f66e611a
...
...
@@ -38,7 +38,7 @@ class Backend(implicit val p: XSConfig) extends XSModule
// val fmacExeUnits = Array.tabulate(exuParameters.FmacCnt)(_ => Module(new Fmac))
// val fmiscExeUnits = Array.tabulate(exuParameters.FmiscCnt)(_ => Module(new Fmisc))
// val fmiscDivSqrtExeUnits = Array.tabulate(exuParameters.FmiscDivSqrtCnt)(_ => Module(new FmiscDivSqrt))
val
lsuExeUnits
=
Array
.
tabulate
(
exuParameters
.
StuCnt
)(
_
=>
Module
(
new
MemWrapper
))
val
lsuExeUnits
=
Array
.
tabulate
(
exuParameters
.
StuCnt
)(
_
=>
Module
(
new
LsExeUnit
))
val
exeUnits
=
jmpExeUnit
+:
(
aluExeUnits
++
mulExeUnits
++
mduExeUnits
++
lsuExeUnits
)
exeUnits
.
foreach
(
_
.
io
.
dmem
:=
DontCare
)
exeUnits
.
foreach
(
_
.
io
.
mcommit
:=
DontCare
)
...
...
@@ -121,11 +121,11 @@ class Backend(implicit val p: XSConfig) extends XSModule
iq
.
io
.
bypassUops
<>
bypassQueues
.
map
(
_
.
io
.
selectedUop
)
})
lsuExeUnits
.
foreach
(
_
.
io
.
dmem
<>
DontCare
)
// TODO
lsuExeUnits
.
foreach
(
_
.
io
.
mcommit
<>
roq
.
io
.
mcommit
)
io
.
mem
.
mcommit
:=
roq
.
io
.
mcommit
io
.
mem
.
ldin
<>
lsuExeUnits
(
0
).
io
.
ldReq
io
.
mem
.
stin
<>
lsuExeUnits
(
0
).
io
.
stReq
lsuExeUnits
(
0
).
io
.
wbReq
<>
io
.
mem
.
out
io
.
mem
.
ldin
:=
DontCare
// TODO
io
.
mem
.
stin
:=
DontCare
// TODO
io
.
frontend
.
redirectInfo
<>
redirectInfo
io
.
frontend
.
commits
<>
roq
.
io
.
commits
...
...
src/main/scala/xiangshan/backend/exu/Exu.scala
浏览文件 @
f66e611a
...
...
@@ -49,10 +49,10 @@ case class ExuConfig
}
}
abstract
class
Exu
[
T
<:
ExuIO
](
val
config
:
ExuConfig
,
gen
:
T
=
new
ExuIO
)
extends
XSModule
{
val
io
=
IO
(
gen
)
abstract
class
Exu
(
val
config
:
ExuConfig
)
extends
XSModule
{
val
io
=
IO
(
new
ExuIO
)
io
.
dmem
<>
DontCare
io
.
out
.
bits
.
debug
:=
DontCare
io
.
out
.
bits
.
debug
.
isMMIO
:=
false
.
B
}
object
Exu
{
...
...
src/main/scala/xiangshan/backend/exu/LsExeUnit.scala
浏览文件 @
f66e611a
...
...
@@ -23,36 +23,6 @@ class StoreQueueEntry extends XSBundle{
val
brTag
=
new
BrqPtr
//FIXIT
}
class
MemWrapperIO
extends
ExuIO
{
val
ldReq
=
Vec
(
2
,
DecoupledIO
(
new
ExuInput
))
val
stReq
=
Vec
(
2
,
DecoupledIO
(
new
ExuInput
))
val
wbReq
=
Vec
(
4
,
Flipped
(
DecoupledIO
(
new
ExuOutput
)))
}
class
MemWrapper
extends
Exu
(
Exu
.
lsuExeUnitCfg
,
new
MemWrapperIO
)
{
val
inLoad
=
io
.
in
.
valid
&&
LSUOpType
.
isLoad
(
io
.
in
.
bits
.
uop
.
ctrl
.
fuOpType
)
val
inStore
=
io
.
in
.
valid
&&
LSUOpType
.
isStore
(
io
.
in
.
bits
.
uop
.
ctrl
.
fuOpType
)
io
.
ldReq
(
0
).
valid
:=
inLoad
io
.
ldReq
(
0
).
bits
:=
io
.
in
.
bits
io
.
ldReq
(
1
)
<>
DontCare
io
.
stReq
(
0
).
valid
:=
inStore
io
.
stReq
(
0
).
bits
:=
io
.
in
.
bits
io
.
stReq
(
1
)
<>
DontCare
io
.
in
.
ready
:=
Mux
(
inLoad
,
io
.
ldReq
(
0
).
ready
,
Mux
(
inStore
,
io
.
stReq
(
0
).
ready
,
true
.
B
))
val
arb
=
Module
(
new
Arbiter
(
new
ExuOutput
,
4
))
arb
.
io
.
in
<>
io
.
wbReq
io
.
out
<>
arb
.
io
.
out
}
// Multi-cycle LSU ported from NOOP
class
LsExeUnit
extends
Exu
(
Exu
.
lsuExeUnitCfg
){
...
...
src/main/scala/xiangshan/backend/package.scala
浏览文件 @
f66e611a
...
...
@@ -117,7 +117,6 @@ package object backend {
def
isStore
(
func
:
UInt
)
:
Bool
=
func
(
3
)
def
isAtom
(
func
:
UInt
)
:
Bool
=
func
(
5
)
def
isLoad
(
func
:
UInt
)
:
Bool
=
!
isStore
(
func
)
&&
!
isAtom
(
func
)
def
atomW
=
"010"
.
U
def
atomD
=
"011"
.
U
...
...
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