btb: add read and write bypass

src/main/scala/xiangshan/frontend/BPU.scala

@@ -210,8 +210,10 @@ class BPUStage2 extends XSModule {
   val inLatch = RegInit(0.U.asTypeOf(io.in.bits))
   when (io.in.fire()) { inLatch := io.in.bits }
   val validLatch = RegInit(false.B)
-  when (io.in.fire()) {
-    validLatch := !io.flush
+  when (io.flush) {
+    validLatch := false.B
+  }.elsewhen (io.in.fire()) {
+    validLatch := true.B
   }.elsewhen (io.out.fire()) {
     validLatch := false.B
   }
@@ -249,12 +251,14 @@ class BPUStage3 extends XSModule {
   val inLatch = RegInit(0.U.asTypeOf(io.in.bits))
   val validLatch = RegInit(false.B)
   when (io.in.fire()) { inLatch := io.in.bits }
-  when (io.in.fire()) {
-    validLatch := !io.flush
+  when (io.flush) {
+    validLatch := false.B
+  }.elsewhen (io.in.fire()) {
+    validLatch := true.B
   }.elsewhen (io.out.valid) {
     validLatch := false.B
   }
-  io.out.valid := validLatch && io.predecode.valid && !flushS3
+  io.out.valid := validLatch && io.predecode.valid && !flushS3 && !io.flush
   io.in.ready := !validLatch || io.out.valid
 
   // RAS

src/main/scala/xiangshan/frontend/btb.scala

@@ -201,6 +201,8 @@ class BTB extends XSModule {
         btbData(w)(b).io.w.req.bits.setIdx := updateBankIdx
         btbData(w)(b).io.w.req.bits.waymask.map(_ := updateWaymask)
         btbData(w)(b).io.w.req.bits.data := btbDataWrite
+        XSDebug(btbWriteValid, "write btb: setIdx=%x meta.tag=%x updateWaymask=%d target=%x _type=%b predCtr=%b\n",
+          updateBankIdx, btbMetaWrite.tag, updateWaymask, btbDataWrite.target, btbDataWrite._type, btbDataWrite.pred)
       }.otherwise {
         btbMeta(w)(b).io.w.req.valid := false.B
         btbMeta(w)(b).io.w.req.bits.setIdx := DontCare
@@ -213,6 +215,20 @@ class BTB extends XSModule {
     }
   }
 
+  // write and read bypass
+  for ( w <- 0 until BtbWays) {
+    for (b <- 0 until BtbBanks) {
+      when (RegNext(updateBank) === btbAddr.getBank(io.in.pcLatch) && RegNext(updateBankIdx) === btbAddr.getBankIdx(io.in.pcLatch)) {
+        when (RegNext(btbWriteValid && io.in.pc.valid) && w.U === RegNext(u.writeWay) && b.U === RegNext(updateBank)) {
+          metaRead(u.writeWay) := RegNext(btbMetaWrite)
+          (0 until FetchWidth).map(i => dataRead(RegNext(u.writeWay))(i.U) := Mux(RegNext(updateWaymask(i)), RegNext(btbDataWrite), btbData(w)(b).io.r.resp.data(i)))
+
+          XSDebug(true.B, "BTB write & read bypass hit!\n")
+        }
+      }
+    }
+  }
+
   io.out.hit := hit
   io.out.taken := isTaken
   io.out.takenIdx := takenIdx