Revert "Ibuf"

src/main/scala/xiangshan/Bundle.scala

@@ -8,7 +8,7 @@ import xiangshan.backend.rename.FreeListPtr
 // Fetch FetchWidth x 32-bit insts from Icache
 class FetchPacket extends XSBundle {
   val instrs = Vec(FetchWidth, UInt(32.W))
-  val mask = UInt((FetchWidth*2).W)
+  val mask = UInt(FetchWidth.W)
   val pc = UInt(VAddrBits.W) // the pc of first inst in the fetch group
 }
 

src/main/scala/xiangshan/frontend/FakeIFU.scala

@@ -69,7 +69,7 @@ class FakeIFU extends XSModule with HasIFUConst {
   fakeCache.io.addr := pc
 
   io.fetchPacket.valid := !io.redirect.valid
-  io.fetchPacket.bits.mask := Fill(FetchWidth*2, 1.U(1.W)) << pc(log2Up(FetchWidth*2), 1)
+  io.fetchPacket.bits.mask := Fill(FetchWidth, 1.U(1.W)) << pc(2+log2Up(FetchWidth)-1, 2)
   io.fetchPacket.bits.pc := pc
   io.fetchPacket.bits.instrs := fakeCache.io.rdata
 

src/main/scala/xiangshan/frontend/Ibuffer.scala

@@ -27,10 +27,6 @@ class Ibuffer extends XSModule {
     io.out(i).bits.isBr := DontCare
   }
 
-  //mask initial
-//  val mask = Wire(Vec(FetchWidth*2, false.B))
-//  (0 until 16).map(i => mask(i.U) := (io.in.bits.pc(4,1) <= i.U))
-
   // ibuf define
   val ibuf = RegInit(VecInit(Seq.fill(IBufSize*2)(0.U(16.W))))
   val ibuf_pc = RegInit(VecInit(Seq.fill(IBufSize*2)(0.U(VAddrBits.W))))
@@ -46,8 +42,6 @@ class Ibuffer extends XSModule {
   val enqValid = !io.flush && io.in.valid && !full && !ibuf_valid(tail_ptr + (FetchWidth*2).U)
   val deqValid = !io.flush && !empty //&& io.out.map(_.ready).reduce(_||_)
 
-  XSWarn(empty, "Ibuffer is empty\n")
-  XSWarn(full, "Ibuffer is full\n")
   io.in.ready := enqValid
 
   // enque
@@ -55,15 +49,20 @@ class Ibuffer extends XSModule {
     XSInfo("Enque start\n")
 
     var enq_idx = 0.U(log2Up(FetchWidth*2+1).W)
-    for(i <- 0 until FetchWidth*2) {
+    for(i <- 0 until FetchWidth) {
       when(io.in.bits.mask(i)) {
-        ibuf(tail_ptr + enq_idx) := Mux(i.U(0), io.in.bits.instrs(i>>1)(31,16), io.in.bits.instrs(i>>1)(15,0))
-        ibuf_pc(tail_ptr + enq_idx) := io.in.bits.pc + enq_idx<<1
+        ibuf(tail_ptr + enq_idx) := io.in.bits.instrs(i)(15,0)
+        ibuf_pc(tail_ptr + enq_idx) := io.in.bits.pc + enq_idx + enq_idx
         ibuf_valid(tail_ptr + enq_idx) := true.B
 
-        XSDebug("Enque: %b\n", Mux(i.U(0), io.in.bits.instrs(i>>1)(31,16), io.in.bits.instrs(i>>1)(15,0)))
+        ibuf(tail_ptr + enq_idx+1.U) := io.in.bits.instrs(i)(31,16)
+        ibuf_pc(tail_ptr + enq_idx+1.U) := io.in.bits.pc + enq_idx + enq_idx + 2.U
+        ibuf_valid(tail_ptr + enq_idx+1.U) := true.B
+
+        XSDebug("Enque: %b\n", io.in.bits.instrs(i)(15,0))
+        XSDebug("Enque: %b\n", io.in.bits.instrs(i)(31,16))
       }
-      enq_idx = enq_idx + io.in.bits.mask(i)
+      enq_idx = enq_idx + io.in.bits.mask(i) + io.in.bits.mask(i)
     }
 
     tail_ptr := tail_ptr + enq_idx
@@ -83,10 +82,8 @@ class Ibuffer extends XSModule {
           // is RVC
           io.out(i).bits.instr := Cat(0.U(16.W), ibuf(head_ptr + deq_idx))
           io.out(i).bits.pc := ibuf_pc(head_ptr + deq_idx)
-
           XSDebug("%b[RVC] PC=%d\n", Cat(0.U(16.W), ibuf(head_ptr + deq_idx)), ibuf_pc(head_ptr + deq_idx))
 
-
           io.out(i).bits.isRVC := true.B
           io.out(i).valid := true.B
           ibuf_valid(head_ptr + deq_idx) := false.B
@@ -94,10 +91,8 @@ class Ibuffer extends XSModule {
           // isn't RVC
           io.out(i).bits.instr := Cat(ibuf(head_ptr + deq_idx+1.U), ibuf(head_ptr + deq_idx))
           io.out(i).bits.pc := ibuf_pc(head_ptr + deq_idx)
-
           XSDebug("%b[NORVC] PC=%d\n", Cat(ibuf(head_ptr + deq_idx+1.U), ibuf(head_ptr + deq_idx)), ibuf_pc(head_ptr + deq_idx))
 
-
           io.out(i).bits.isRVC := false.B
           io.out(i).valid := true.B
           ibuf_valid(head_ptr + deq_idx) := false.B
@@ -124,16 +119,10 @@ class Ibuffer extends XSModule {
       // when RVC deque, deq_idx+1
       // when not RVC deque, deq_idx+2
       // when only have half inst, keep it in buffer
-      //deq_idx = deq_idx +
-      //          (io.out(i).ready && ibuf_valid(head_ptr + deq_idx) && ibuf(head_ptr + deq_idx)(1,0) =/= "b11".U) +
-      //          (io.out(i).ready && ibuf_valid(head_ptr + deq_idx) && !(ibuf(head_ptr + deq_idx)(1,0) =/= "b11".U) && ibuf_valid(head_ptr + deq_idx + 1.U)) +
-      //          (io.out(i).ready && ibuf_valid(head_ptr + deq_idx) && !(ibuf(head_ptr + deq_idx)(1,0) =/= "b11".U) && ibuf_valid(head_ptr + deq_idx + 1.U))
-
-      deq_idx = deq_idx + PriorityMux(Seq(
-        !(io.out(i).ready && ibuf_valid(head_ptr + deq_idx)) -> 0.U,
-        (ibuf(head_ptr + deq_idx)(1,0) =/= "b11".U) -> 1.U,
-        ibuf_valid(head_ptr + deq_idx + 1.U) -> 2.U
-      ))
+      deq_idx = deq_idx +
+                (io.out(i).ready && ibuf_valid(head_ptr + deq_idx) && ibuf(head_ptr + deq_idx)(1,0) =/= "b11".U) +
+                (io.out(i).ready && ibuf_valid(head_ptr + deq_idx) && !(ibuf(head_ptr + deq_idx)(1,0) =/= "b11".U) && ibuf_valid(head_ptr + deq_idx + 1.U)) +
+                (io.out(i).ready && ibuf_valid(head_ptr + deq_idx) && !(ibuf(head_ptr + deq_idx)(1,0) =/= "b11".U) && ibuf_valid(head_ptr + deq_idx + 1.U))
     }
     head_ptr := head_ptr + deq_idx