dispatch2: add ls logic

src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala

@@ -44,7 +44,18 @@ class Dispatch2Int extends XSModule {
   val validVec = allIndexGen.map(_.io.mapping.map(_.valid)).reduceLeft(_ ++ _)
   val indexVec = allIndexGen.map(_.io.mapping.map(_.bits)).reduceLeft(_ ++ _)
   val rsValidVec = allIndexGen.map(_.io.reverseMapping.map(_.valid)).reduceLeft(_ ++ _)
-  val rsIndexVec = allIndexGen.map(_.io.reverseMapping.map(_.bits)).reduceLeft(_ ++ _)
+  val rsIndexVecRaw = allIndexGen.map(_.io.reverseMapping.map(_.bits)).reduceLeft(_ ++ _)
+  val rsIndexVec = rsIndexVecRaw.zipWithIndex.map{ case (index, i) =>
+    (if (i >= exuParameters.JmpCnt + exuParameters.AluCnt) {
+      index + exuParameters.JmpCnt.U + exuParameters.AluCnt.U
+    }
+    else if (i >= exuParameters.JmpCnt) {
+      index + exuParameters.JmpCnt.U
+    }
+    else {
+      index
+    })
+  }
 
   /**
     * Part 2: assign regfile read ports
@@ -73,10 +84,10 @@ class Dispatch2Int extends XSModule {
     enq.valid := validVec(i)
     enq.bits := io.fromDq(indexVec(i)).bits
     enq.bits.src1State := io.regRdy(readPortIndex(i))
-    enq.bits.src1State := io.regRdy(readPortIndex(i) + 1.U)
+    enq.bits.src2State := io.regRdy(readPortIndex(i) + 1.U)
 
-    XSInfo(enq.fire(), p"pc 0x${Hexadecimal(enq.bits.cf.pc)} with type ${enq.bits.ctrl.fuType}" +
-      p"srcState(${enq.bits.src1State} ${enq.bits.src2State} ${enq.bits.src3State})" +
+    XSInfo(enq.fire(), p"pc 0x${Hexadecimal(enq.bits.cf.pc)} with type ${enq.bits.ctrl.fuType} " +
+      p"srcState(${enq.bits.src1State} ${enq.bits.src2State}) " +
       p"enters reservation station $i from ${indexVec(i)}\n")
   }
 
@@ -89,7 +100,7 @@ class Dispatch2Int extends XSModule {
     XSInfo(io.fromDq(i).fire(),
       p"pc 0x${Hexadecimal(io.fromDq(i).bits.cf.pc)} leaves Int dispatch queue $i with nroq ${io.fromDq(i).bits.roqIdx}\n")
     XSDebug(io.fromDq(i).valid && !io.fromDq(i).ready,
-      p"pc 0x${Hexadecimal(io.fromDq(i).bits.cf.pc)} waits at Int dispatch queue with index %d\n")
+      p"pc 0x${Hexadecimal(io.fromDq(i).bits.cf.pc)} waits at Int dispatch queue with index $i\n")
   }
 
   /**

src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala

+package xiangshan.backend.dispatch
+
+import chisel3._
+import chisel3.util._
+import xiangshan._
+import utils._
+import xiangshan.backend.regfile.RfReadPort
+import xiangshan.backend.exu._
+
+class Dispatch2Ls extends XSModule {
+  val io = IO(new Bundle() {
+    val fromDq = Flipped(Vec(dpParams.LsDqDeqWidth, DecoupledIO(new MicroOp)))
+    val intRegAddr = Vec(NRMemReadPorts, Output(UInt(PhyRegIdxWidth.W)))
+    val fpRegAddr = Vec(exuParameters.StuCnt, Output(UInt(PhyRegIdxWidth.W)))
+    val intRegRdy = Vec(NRMemReadPorts, Input(Bool()))
+    val fpRegRdy = Vec(exuParameters.StuCnt, Input(Bool()))
+    val numExist = Input(Vec(exuParameters.LsExuCnt, UInt(log2Ceil(IssQueSize).W)))
+    val enqIQCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp))
+  })
+
+  /**
+    * Part 1: generate indexes for reservation stations
+    */
+  val loadIndexGen = Module(new IndexMapping(dpParams.LsDqDeqWidth, exuParameters.LduCnt, true))
+  val storeIndexGen = Module(new IndexMapping(dpParams.LsDqDeqWidth, exuParameters.StuCnt, true))
+  val loadPriority = PriorityGen((0 until exuParameters.LduCnt).map(i => io.numExist(i)))
+  val storePriority = PriorityGen((0 until exuParameters.StuCnt).map(i => io.numExist(i+exuParameters.LduCnt)))
+  for (i <- 0 until dpParams.LsDqDeqWidth) {
+    loadIndexGen.io.validBits(i) := Exu.ldExeUnitCfg.canAccept(io.fromDq(i).bits.ctrl.fuType)
+    storeIndexGen.io.validBits(i) := Exu.stExeUnitCfg.canAccept(io.fromDq(i).bits.ctrl.fuType)
+
+    XSDebug(io.fromDq(i).valid,
+      p"ls dp queue $i: ${Hexadecimal(io.fromDq(i).bits.cf.pc)} type ${Binary(io.fromDq(i).bits.ctrl.fuType)}\n")
+  }
+  for (i <- 0 until exuParameters.LduCnt) {
+    loadIndexGen.io.priority(i) := loadPriority(i)
+  }
+  for (i <- 0 until exuParameters.StuCnt) {
+    storeIndexGen.io.priority(i) := storePriority(i)
+  }
+  val allIndexGen = Seq(loadIndexGen, storeIndexGen)
+  val validVec = allIndexGen.map(_.io.mapping.map(_.valid)).reduceLeft(_ ++ _)
+  val indexVec = allIndexGen.map(_.io.mapping.map(_.bits)).reduceLeft(_ ++ _)
+  val rsValidVec = allIndexGen.map(_.io.reverseMapping.map(_.valid)).reduceLeft(_ ++ _)
+  val rsIndexVec = allIndexGen.map(_.io.reverseMapping.map(_.bits)).reduceLeft(_ ++ _)
+
+  /**
+    * Part 2: assign regfile read ports (actually only reg states from rename)
+    *
+    * The four load/store issue queue
+    */
+  assert(exuParameters.LduCnt == 2)
+  assert(exuParameters.StuCnt == 2)
+  val readPort = Seq(0, 1, 2, 4)
+  for (i <- 0 until exuParameters.LsExuCnt) {
+    if (i < exuParameters.LduCnt) {
+      io.intRegAddr(readPort(i)) := io.fromDq(indexVec(i)).bits.psrc1
+    }
+    else {
+      io.intRegAddr(readPort(i)) := io.fromDq(indexVec(i)).bits.psrc1
+      io.intRegAddr(readPort(i) + 1) := io.fromDq(indexVec(i)).bits.psrc2
+    }
+  }
+
+  /**
+    * Part 3: dispatch to reservation stations
+    */
+  for (i <- 0 until exuParameters.LsExuCnt) {
+    val enq = io.enqIQCtrl(i)
+    enq.valid := validVec(i)
+    enq.bits := io.fromDq(indexVec(i)).bits
+    enq.bits.src1State := io.intRegRdy(readPort(i))
+    enq.bits.src2State := io.intRegRdy(readPort(i) + 1)
+
+    XSInfo(enq.fire(), p"pc 0x${Hexadecimal(enq.bits.cf.pc)} with type ${enq.bits.ctrl.fuType}" +
+      p"srcState(${enq.bits.src1State} ${enq.bits.src2State})" +
+      p"enters reservation station $i from ${indexVec(i)}\n")
+  }
+
+  /**
+    * Part 4: response to dispatch queue
+    */
+  for (i <- 0 until dpParams.LsDqDeqWidth) {
+    io.fromDq(i).ready := rsValidVec(i) && io.enqIQCtrl(rsIndexVec(i)).ready
+
+    XSInfo(io.fromDq(i).fire(),
+      p"pc 0x${Hexadecimal(io.fromDq(i).bits.cf.pc)} leaves Int dispatch queue $i with nroq ${io.fromDq(i).bits.roqIdx}\n")
+    XSDebug(io.fromDq(i).valid && !io.fromDq(i).ready,
+      p"pc 0x${Hexadecimal(io.fromDq(i).bits.cf.pc)} waits at Int dispatch queue with index %d\n")
+  }
+}
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