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体验新版 GitCode,发现更多精彩内容 >>
提交
f012b01b
编写于
6月 25, 2020
作者:
J
jinyue
浏览文件
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差异文件
Merge branch 'master' into issuequeue
上级
2fe21c3e
48599901
变更
3
隐藏空白更改
内联
并排
Showing
3 changed file
with
82 addition
and
7 deletion
+82
-7
src/main/scala/xiangshan/backend/brq/Brq.scala
src/main/scala/xiangshan/backend/brq/Brq.scala
+20
-0
src/main/scala/xiangshan/backend/rename/Rename.scala
src/main/scala/xiangshan/backend/rename/Rename.scala
+31
-0
src/main/scala/xiangshan/backend/roq/Roq.scala
src/main/scala/xiangshan/backend/roq/Roq.scala
+31
-7
未找到文件。
src/main/scala/xiangshan/backend/brq/Brq.scala
浏览文件 @
f012b01b
...
...
@@ -3,6 +3,7 @@ package xiangshan.backend.brq
import
chisel3._
import
chisel3.util._
import
xiangshan._
import
xiangshan.utils.XSInfo
...
...
@@ -78,4 +79,23 @@ class Brq extends XSModule {
headPtr
:=
0.
U
tailPtr
:=
0.
U
}
// Debug info
val
debug_roq_redirect
=
io
.
roqRedirect
.
valid
val
debug_brq_redirect
=
io
.
redirect
.
valid
&&
!
debug_roq_redirect
val
debug_normal_mode
=
!(
debug_roq_redirect
||
debug_brq_redirect
)
for
(
i
<-
0
until
DecodeWidth
){
XSInfo
(
debug_normal_mode
,
p
"enq v:${io.enqReqs(i).valid} rdy:${io.enqReqs(i).ready} pc:${Hexadecimal(io.enqReqs(i).bits.cf.pc)}"
+
p
" brMask:${Binary(io.brMasks(i))} brTag:${io.brTags(i)}\n"
)
}
XSInfo
(
debug_roq_redirect
,
"roq redirect, flush brq\n"
)
XSInfo
(
debug_brq_redirect
,
p
"brq redirect, target:${Hexadecimal(io.redirect.bits.target)}\n"
)
}
src/main/scala/xiangshan/backend/rename/Rename.scala
浏览文件 @
f012b01b
...
...
@@ -3,6 +3,7 @@ package xiangshan.backend.rename
import
chisel3._
import
chisel3.util._
import
xiangshan._
import
xiangshan.utils.XSInfo
class
Rename
extends
XSModule
{
val
io
=
IO
(
new
Bundle
()
{
...
...
@@ -20,6 +21,26 @@ class Rename extends XSModule {
val
out
=
Vec
(
RenameWidth
,
DecoupledIO
(
new
MicroOp
))
})
val
debug_exception
=
io
.
redirect
.
valid
&&
io
.
redirect
.
bits
.
isException
val
debug_walk
=
io
.
roqCommits
.
map
(
_
.
bits
.
isWalk
).
reduce
(
_
||
_
)
val
debug_norm
=
!(
debug_exception
||
debug_walk
)
def
printRenameInfo
(
in
:
DecoupledIO
[
CfCtrl
],
out
:
DecoupledIO
[
MicroOp
])
=
{
XSInfo
(
debug_norm
,
p
"pc:${Hexadecimal(in.bits.cf.pc)} v:${in.valid} rdy:${in.ready} "
+
p
"lsrc1:${in.bits.ctrl.lsrc1} -> psrc1:${out.bits.psrc1} "
+
p
"lsrc2:${in.bits.ctrl.lsrc2} -> psrc2:${out.bits.psrc2} "
+
p
"lsrc3:${in.bits.ctrl.lsrc3} -> psrc3:${out.bits.psrc3} "
+
p
"ldest:${in.bits.ctrl.ldest} -> pdest:${out.bits.pdest} "
+
p
"old_pdest:${out.bits.old_pdest}\n"
)
}
for
((
x
,
y
)
<-
io
.
in
.
zip
(
io
.
out
)){
printRenameInfo
(
x
,
y
)
}
val
fpFreeList
,
intFreeList
=
Module
(
new
FreeList
).
io
val
fpRat
=
Module
(
new
RenameTable
(
float
=
true
)).
io
val
intRat
=
Module
(
new
RenameTable
(
float
=
false
)).
io
...
...
@@ -85,10 +106,20 @@ class Rename extends XSModule {
rat
.
specWritePorts
(
i
).
addr
:=
Mux
(
specWen
,
uops
(
i
).
ctrl
.
ldest
,
io
.
roqCommits
(
i
).
bits
.
uop
.
ctrl
.
ldest
)
rat
.
specWritePorts
(
i
).
wdata
:=
Mux
(
specWen
,
freeList
.
pdests
(
i
),
io
.
roqCommits
(
i
).
bits
.
uop
.
old_pdest
)
XSInfo
(
walkWen
,
{
if
(
fp
)
"fp"
else
"int "
}
+
p
"walk: pc:${Hexadecimal(uops(i).cf.pc)}"
+
p
" ldst:${rat.specWritePorts(i).addr} old_pdest:${rat.specWritePorts(i).wdata}\n"
)
rat
.
archWritePorts
(
i
).
wen
:=
commitDestValid
&&
!
io
.
roqCommits
(
i
).
bits
.
isWalk
rat
.
archWritePorts
(
i
).
addr
:=
io
.
roqCommits
(
i
).
bits
.
uop
.
ctrl
.
ldest
rat
.
archWritePorts
(
i
).
wdata
:=
io
.
roqCommits
(
i
).
bits
.
uop
.
pdest
XSInfo
(
rat
.
archWritePorts
(
i
).
wen
,
{
if
(
fp
)
"fp"
else
"int "
}
+
p
" rat arch: ldest:${rat.archWritePorts(i).addr}"
+
p
" pdest:${rat.archWritePorts(i).wdata}\n"
)
freeList
.
deallocReqs
(
i
)
:=
rat
.
archWritePorts
(
i
).
wen
freeList
.
deallocPregs
(
i
)
:=
io
.
roqCommits
(
i
).
bits
.
uop
.
old_pdest
...
...
src/main/scala/xiangshan/backend/roq/Roq.scala
浏览文件 @
f012b01b
...
...
@@ -3,6 +3,7 @@ package xiangshan.backend.roq
import
chisel3._
import
chisel3.util._
import
xiangshan._
import
xiangshan.utils._
import
chisel3.util.experimental.BoringUtils
// A "just-enough" Roq
...
...
@@ -42,18 +43,24 @@ class Roq(implicit val p: XSConfig) extends XSModule {
// Dispatch
val
validDispatch
=
VecInit
((
0
until
RenameWidth
).
map
(
io
.
dp1Req
(
_
).
valid
)).
asUInt
XSDebug
(
"(ready, valid): "
)
for
(
i
<-
0
until
RenameWidth
){
val
offset
=
if
(
i
==
0
)
0.
U
else
PopCount
(
validDispatch
(
i
-
1
,
0
))
when
(
io
.
dp1Req
(
i
).
fire
()){
microOp
(
ringBufferHead
+
offset
)
:=
io
.
dp1Req
(
i
).
bits
valid
(
ringBufferHead
+
offset
)
:=
true
.
B
writebacked
(
ringBufferHead
+
offset
)
:=
false
.
B
}
io
.
dp1Req
(
i
).
ready
:=
ringBufferAllowin
&&
!
valid
(
ringBufferHead
+
offset
)
&&
state
===
s_idle
io
.
roqIdxs
(
i
)
:=
ringBufferHeadExtended
+
offset
XSDebug
(){
printf
(
"(%d, %d) "
,
io
.
dp1Req
(
i
).
ready
,
io
.
dp1Req
(
i
).
valid
)}
}
XSDebug
(){
printf
(
"\n"
)}
val
firedDispatch
=
VecInit
((
0
until
CommitWidth
).
map
(
io
.
dp1Req
(
_
).
fire
())).
asUInt
when
(
validDispatch
.
orR
){
ringBufferHeadExtended
:=
ringBufferHeadExtended
+
PopCount
(
validDispatch
)
when
(
firedDispatch
.
orR
){
ringBufferHeadExtended
:=
ringBufferHeadExtended
+
PopCount
(
firedDispatch
)
XSInfo
(
"dispatched %d insts\n"
,
PopCount
(
firedDispatch
))
}
// Writeback
...
...
@@ -64,14 +71,19 @@ class Roq(implicit val p: XSConfig) extends XSModule {
exuDebug
(
io
.
exeWbResults
(
i
).
bits
.
uop
.
roqIdx
)
:=
io
.
exeWbResults
(
i
).
bits
.
debug
}
}
val
firedWriteback
=
VecInit
((
0
until
exuConfig
.
ExuCnt
).
map
(
io
.
exeWbResults
(
_
).
fire
())).
asUInt
when
(
PopCount
(
firedWriteback
)
>
0.
U
){
XSInfo
(
"writebacked %d insts\n"
,
PopCount
(
firedWriteback
))
}
// Commit uop to Rename
for
(
i
<-
0
until
CommitWidth
){
when
(
state
===
s_idle
){
io
.
commits
(
i
).
valid
:=
valid
(
ringBufferTail
+
i
.
U
)
&&
writebacked
(
ringBufferTail
+
i
.
U
)
val
canCommit
=
if
(
i
!=
0
)
io
.
commits
(
i
-
1
).
valid
else
true
.
B
io
.
commits
(
i
).
valid
:=
valid
(
ringBufferTail
+
i
.
U
)
&&
writebacked
(
ringBufferTail
+
i
.
U
)
&&
canCommit
io
.
commits
(
i
).
bits
.
uop
:=
microOp
(
ringBufferTail
+
i
.
U
)
when
(
microOp
(
i
).
ctrl
.
rfWen
){
archRF
(
microOp
(
i
).
ctrl
.
ldest
)
:=
exuData
(
i
)
}
when
(
valid
(
ringBufferTail
+
i
.
U
)){
valid
(
ringBufferTail
+
i
.
U
)
:=
false
.
B
}
//FIXIT
when
(
io
.
commits
(
i
).
valid
){
valid
(
ringBufferTail
+
i
.
U
)
:=
false
.
B
}
}.
otherwise
{
//state === s_walk
io
.
commits
(
i
).
valid
:=
valid
(
ringBufferWalk
+
i
.
U
)
&&
writebacked
(
ringBufferWalk
+
i
.
U
)
io
.
commits
(
i
).
bits
.
uop
:=
microOp
(
ringBufferWalk
+
i
.
U
)
...
...
@@ -85,6 +97,8 @@ class Roq(implicit val p: XSConfig) extends XSModule {
ringBufferTailExtended
:=
ringBufferTailExtended
+
PopCount
(
validCommit
)
}
val
retireCounter
=
Mux
(
state
===
s_idle
,
PopCount
(
validCommit
),
0.
U
)
// TODO: commit store
XSInfo
(
retireCounter
>
0.
U
,
"retired %d insts\n"
,
retireCounter
)
val
walkFinished
=
(
0
until
CommitWidth
).
map
(
i
=>
(
ringBufferWalk
+
i
.
U
)
===
ringBufferWalkTarget
).
reduce
(
_
||
_
)
...
...
@@ -94,9 +108,7 @@ class Roq(implicit val p: XSConfig) extends XSModule {
state
:=
s_idle
}
ringBufferWalkExtended
:=
ringBufferWalkExtended
+
CommitWidth
.
U
// Debug(){
printf
(
"[ROQ] rolling back: head %d tail %d walk %d\n"
,
ringBufferHead
,
ringBufferTail
,
ringBufferWalk
)
// }
XSInfo
(
"rolling back: head %d tail %d walk %d\n"
,
ringBufferHead
,
ringBufferTail
,
ringBufferWalk
)
}
when
(
io
.
brqRedirect
.
valid
){
...
...
@@ -110,6 +122,18 @@ class Roq(implicit val p: XSConfig) extends XSModule {
io
.
redirect
:=
DontCare
//TODO
io
.
redirect
.
valid
:=
false
.
B
//TODO
// debug info
XSDebug
(
"head %d tail %d\n"
,
ringBufferHead
,
ringBufferTail
)
XSDebug
(
""
)
XSDebug
(){
for
(
i
<-
0
until
RoqSize
){
when
(!
valid
(
i
)){
printf
(
"-"
)}
when
(
valid
(
i
)
&&
writebacked
(
i
)){
printf
(
"w"
)}
when
(
valid
(
i
)
&&
!
writebacked
(
i
)){
printf
(
"v"
)}
}
printf
(
"\n"
)
}
//difftest signals
val
firstValidCommit
=
ringBufferTail
+
PriorityMux
(
validCommit
,
VecInit
(
List
.
tabulate
(
CommitWidth
)(
_
.
U
)))
val
emptyCsr
=
WireInit
(
0.
U
(
64.
W
))
...
...
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