func(fuBusyTable): add fuBusyTable with resp

func(IQ): add fuBusyTable

func(IssueQueue): suppport fuBusyTable write with og0Resp & og1Resp

func(RSFeedbackType): delete issueFail/rfArbitFail in RSFeedbackType

func(Fu):make some FuncUnits piped

fix(fuBusyTable): fix write of fuBusyTable

type(fuBusyTable): rename & delete some comments

src/main/scala/xiangshan/Bundle.scala

@@ -50,11 +50,9 @@ object RSFeedbackType {
   val ldVioCheckRedo  = 4.U(4.W)
   val feedbackInvalid = 7.U(4.W)
   val issueSuccess    = 8.U(4.W)
-  val issueFail       = 9.U(4.W)
-  val rfArbitSuccess  = 10.U(4.W)
-  val rfArbitFail     = 11.U(4.W)
-  val fuIdle          = 12.U(4.W)
-  val fuBusy          = 13.U(4.W)
+  val rfArbitFail     = 9.U(4.W)
+  val fuIdle          = 10.U(4.W)
+  val fuBusy          = 11.U(4.W)
 
   def apply() = UInt(4.W)
 
@@ -63,7 +61,7 @@ object RSFeedbackType {
   }
 
   def isBlocked(feedbackType: UInt) = {
-    feedbackType === issueFail || feedbackType === rfArbitFail || feedbackType === fuBusy || feedbackType === feedbackInvalid
+    feedbackType === rfArbitFail || feedbackType === fuBusy || feedbackType === feedbackInvalid
   }
 }
 

src/main/scala/xiangshan/backend/datapath/DataPath.scala

@@ -229,9 +229,6 @@ class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params
 
   vfRFReadArbiter.io.out.map(_.bits.addr).zip(vfRfRaddr).foreach{ case(source, sink) => sink := source }
 
-  // fromIQFire(i): flattened the i-th deq port fired
-  private val fromIQFire: IndexedSeq[Bool] = fromIQ.flatten.map(_.fire)
-
   intDebugRead.foreach { case (addr, _) =>
     addr := io.debugIntRat
   }
@@ -356,22 +353,22 @@ class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params
     }
   }
 
-  private val intFromIQFire = fromIQ.map(_.map(_.fire))
-  private val intToExuFire = toExu.map(_.map(_.fire))
+  private val fromIQFire = fromIQ.map(_.map(_.fire))
+  private val toExuFire = toExu.map(_.map(_.fire))
   toIQs.zipWithIndex.foreach {
     case(toIQ, iqIdx) =>
       toIQ.zipWithIndex.foreach {
         case (toIU, iuIdx) =>
           // IU: issue unit
           val og0resp = toIU.og0resp
-          og0resp.valid := fromIQ(iqIdx)(iuIdx).valid
-          og0resp.bits.respType := Mux(intFromIQFire(iqIdx)(iuIdx), RSFeedbackType.rfArbitSuccess, RSFeedbackType.rfArbitFail)
+          og0resp.valid := fromIQ(iqIdx)(iuIdx).valid && (!fromIQFire(iqIdx)(iuIdx))
+          og0resp.bits.respType := RSFeedbackType.rfArbitFail
           og0resp.bits.success := false.B
           og0resp.bits.addrOH := fromIQ(iqIdx)(iuIdx).bits.addrOH
 
           val og1resp = toIU.og1resp
           og1resp.valid := s1_toExuValid(iqIdx)(iuIdx)
-          og1resp.bits.respType := Mux(intToExuFire(iqIdx)(iuIdx), RSFeedbackType.fuIdle, RSFeedbackType.fuBusy)
+          og1resp.bits.respType := Mux(toExuFire(iqIdx)(iuIdx), RSFeedbackType.fuIdle, RSFeedbackType.fuBusy)
           og1resp.bits.success := false.B
           og1resp.bits.addrOH := s1_addrOHs(iqIdx)(iuIdx)
       }

src/main/scala/xiangshan/backend/exu/ExeUnit.scala

@@ -48,6 +48,9 @@ class ExeUnitImp(
   }.elsewhen(io.in.fire) {
     busy := true.B
   }
+  if(exuParams.latencyValMax.nonEmpty){
+    busy := false.B
+  }
 
   // rob flush --> funcUnits
   funcUnits.zipWithIndex.foreach { case (fu, i) =>
@@ -61,7 +64,7 @@ class ExeUnitImp(
   val in1ToN = Module(new Dispatcher(new ExuInput(exuParams), funcUnits.length, acceptCond))
 
   // ExeUnit.in <---> Dispatcher.in
-  in1ToN.io.in.valid := io.in.valid && !busy
+  in1ToN.io.in.valid := io.in.fire()
   in1ToN.io.in.bits := io.in.bits
   io.in.ready := !busy
 
@@ -89,6 +92,7 @@ class ExeUnitImp(
   }
 
   private val fuOutValidOH = funcUnits.map(_.io.out.valid)
+  XSError(PopCount(fuOutValidOH) > 1.U, p"fuOutValidOH ${Binary(VecInit(fuOutValidOH).asUInt)} should be one-hot)\n")
   private val fuOutBitsVec = funcUnits.map(_.io.out.bits)
   private val fuRedirectVec: Seq[Option[ValidIO[Redirect]]] = funcUnits.map(_.io.out.bits.redirect)
 

src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala

@@ -47,6 +47,10 @@ case class ExeUnitParams(
   val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _)
   val wbPregIdxWidth = if (wbPortConfigs.nonEmpty) wbPortConfigs.map(_.pregIdxWidth).max else 0
 
+  protected val latencyCertain = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_&&_)
+  val fuLatencyMap = if (latencyCertain) Some(fuConfigs.map(y => (y.fuType, y.latency.latencyVal.get))) else None
+  val latencyValMax = fuLatencyMap.map(x => x.map(_._2).max)
+
   def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _)
 
   def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _)

src/main/scala/xiangshan/backend/fu/Bku.scala

@@ -359,5 +359,5 @@ class Bku(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) with HasP
                       Mux(funcReg(2),miscModule.io.out, clmulModule.io.out)))
 
   io.out.bits.data := RegEnable(result, regEnable(2))
-  connectNonPipedCtrlSingal
+  // connectNonPipedCtrlSingal
 }

src/main/scala/xiangshan/backend/fu/FuncUnit.scala

@@ -80,6 +80,11 @@ trait HasPipelineReg { this: FuncUnit =>
   val validVec = io.in.valid +: Seq.fill(latency)(RegInit(false.B))
   val rdyVec = Seq.fill(latency)(Wire(Bool())) :+ io.out.ready
   val robIdxVec = io.in.bits.robIdx +: Array.fill(latency)(Reg(chiselTypeOf(io.in.bits.robIdx)))
+  val pdestVec = io.in.bits.pdest +: Array.fill(latency)(Reg(chiselTypeOf(io.in.bits.pdest)))
+
+  val pcVec = io.in.bits.pc.map(x => x) +: Array.fill(latency)( io.in.bits.pc.map(x => Reg(chiselTypeOf(x)))) // Reg(chiselTypeOf(io.in.bits.pc.get))
+  val preDecodeVec = io.in.bits.preDecode.map(x => x) +: Array.fill(latency)(io.in.bits.preDecode.map(x => Reg(chiselTypeOf(x))))
+  val fpuVec = io.in.bits.fpu.map(x => x) +: Array.fill(latency)(io.in.bits.fpu.map(x => Reg(chiselTypeOf(x))))
 
   // if flush(0), valid 0 will not given, so set flushVec(0) to false.B
   val flushVec = validVec.zip(robIdxVec).map(x => x._1 && x._2.needFlush(io.flush))
@@ -92,6 +97,10 @@ trait HasPipelineReg { this: FuncUnit =>
     when(rdyVec(i - 1) && validVec(i - 1) && !flushVec(i - 1)){
       validVec(i) := validVec(i - 1)
       robIdxVec(i) := robIdxVec(i - 1)
+      pdestVec(i) := pdestVec(i - 1)
+      pcVec(i).zip(pcVec(i - 1)).foreach{case (l,r) => l := r}
+      preDecodeVec(i).zip(preDecodeVec(i - 1)).foreach{case (l,r) => l := r}
+      fpuVec(i).zip(fpuVec(i - 1)).foreach{case (l,r) => l := r}
     }.elsewhen(flushVec(i) || rdyVec(i)){
       validVec(i) := false.B
     }
@@ -100,6 +109,10 @@ trait HasPipelineReg { this: FuncUnit =>
   io.in.ready := rdyVec(0)
   io.out.valid := validVec.last
   io.out.bits.robIdx := robIdxVec.last
+  io.out.bits.pdest := pdestVec.last
+  io.out.bits.pc.zip(pcVec.last).foreach{case (l,r) => l := r}
+  io.out.bits.preDecode.zip(preDecodeVec.last).foreach{case (l,r) => l := r}
+  io.out.bits.fpu.zip(fpuVec.last).foreach{case (l,r) => l := r}
 
   def regEnable(i: Int): Bool = validVec(i - 1) && rdyVec(i - 1) && !flushVec(i - 1)
 

src/main/scala/xiangshan/backend/fu/fpu/FPToFP.scala

@@ -126,5 +126,4 @@ class FPToFP(cfg: FuConfig)(implicit p: Parameters) extends FPUPipelineModule(cf
   override val dataModule = Module(new FPToFPDataModule(latency))
   connectDataModule
   dataModule.regEnables <> VecInit((1 to latency) map (i => regEnable(i)))
-  connectNonPipedCtrlSingal // Todo: make it piped
 }

src/main/scala/xiangshan/backend/fu/fpu/FPToInt.scala

@@ -139,5 +139,4 @@ class FPToInt(cfg: FuConfig)(implicit p: Parameters) extends FPUPipelineModule(c
   override val dataModule = Module(new FPToIntDataModule(latency))
   connectDataModule
   dataModule.regEnables <> VecInit((1 to latency) map (i => regEnable(i)))
-  connectNonPipedCtrlSingal // Todo: make it piped
 }

src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala

@@ -82,5 +82,4 @@ class IntToFP(cfg: FuConfig)(implicit p: Parameters) extends FPUPipelineModule(c
   override val dataModule = Module(new IntToFPDataModule(latency))
   connectDataModule
   dataModule.regEnables <> VecInit((1 to latency) map (i => regEnable(i)))
-  connectNonPipedCtrlSingal // Todo: make it piped
 }

src/main/scala/xiangshan/backend/fu/wrapper/MulUnit.scala

@@ -58,5 +58,4 @@ class MulUnit(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg)
   private val res = Mux(ctrlVec.last.isHi, result(2 * xlen - 1, xlen), result(xlen - 1, 0))
 
   io.out.bits.data := Mux(ctrlVec.last.isW, SignExt(res(31, 0), xlen), res)
-  connectNonPipedCtrlSingal // Todo: make it piped
 }

src/main/scala/xiangshan/backend/issue/IssueQueue.scala

@@ -55,7 +55,10 @@ class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, va
 
   require(params.numExu <= 2, "IssueQueue has not supported more than 2 deq ports")
   val deqFuCfgs     : Seq[Seq[FuConfig]] = params.exuBlockParams.map(_.fuConfigs)
-  val allDeqFuCfgs  : Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs)
+  val latencyCertains: Seq[Boolean] = deqFuCfgs.map(x => x.map(x => x.latency.latencyVal.nonEmpty).reduce(_ && _))
+  val fuLatencyMaps :  Seq[Option[Seq[(Int, Int)]]]  = params.exuBlockParams.map(x => x.fuLatencyMap)
+  val latencyValMaxs: Seq[Option[Int]] = params.exuBlockParams.map(x => x.latencyValMax)
+  val allDeqFuCfgs: Seq[FuConfig] = params.exuBlockParams.flatMap(_.fuConfigs)
   val fuCfgsCnt     : Map[FuConfig, Int] = allDeqFuCfgs.groupBy(x => x).map { case (cfg, cfgSeq) => (cfg, cfgSeq.length) }
   val commonFuCfgs  : Seq[FuConfig] = fuCfgsCnt.filter(_._2 > 1).keys.toSeq
   println(s"[IssueQueueImp] ${params.getIQName} commonFuCfgs: ${commonFuCfgs.map(_.name)}")
@@ -68,8 +71,16 @@ class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, va
   val payloadArray  = Module(new DataArray(Output(new DynInst), params.numDeq, params.numEnq, params.numEntries))
   val enqPolicy     = Module(new EnqPolicy)
   val subDeqPolicies  = deqFuCfgs.map(x => if (x.nonEmpty) Some(Module(new DeqPolicy())) else None)
+  val fuBusyTable = latencyValMaxs.map { case y => if (y.getOrElse(0)>0) Some(Reg(UInt(y.getOrElse(1).W))) else None }
 
   // Wires
+  val resps = params.schdType match {
+    case IntScheduler() => Seq(io.deqResp, io.og0Resp, io.og1Resp)
+    case MemScheduler() => Seq(io.deqResp, io.og1Resp)
+    case VfScheduler() => Seq(io.deqResp, io.og1Resp)
+    case _ => null
+  }
+  val fuBusyTableMask = Wire(Vec(params.numDeq, UInt(params.numEntries.W)))
   val s0_enqValidVec = io.enq.map(_.valid)
   val s0_enqSelValidVec = Wire(Vec(params.numEnq, Bool()))
   val s0_enqSelOHVec = Wire(Vec(params.numEnq, UInt(params.numEntries.W)))
@@ -213,7 +224,7 @@ class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, va
   subDeqPolicies.zipWithIndex.map { case (dpOption: Option[DeqPolicy], i) =>
     if (dpOption.nonEmpty) {
       val dp = dpOption.get
-      dp.io.request             := canIssueVec.asUInt & VecInit(deqCanAcceptVec(i)).asUInt
+      dp.io.request             := canIssueVec.asUInt & VecInit(deqCanAcceptVec(i)).asUInt & (~fuBusyTableMask(i)).asUInt()
       subDeqSelValidVec(i).get  := dp.io.deqSelOHVec.map(oh => oh.valid)
       subDeqSelOHVec(i).get     := dp.io.deqSelOHVec.map(oh => oh.bits)
     }
@@ -231,6 +242,67 @@ class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, va
                                   subDeqSelOHVec(1).getOrElse(Seq(0.U)).head)
   }
 
+  // fuBusyTable write
+  for (i <- 0 until params.numDeq){
+    if (fuBusyTable(i).nonEmpty) {
+      val isLatencyNumVec = Mux(resps(0)(i).valid && resps(0)(i).bits.respType === RSFeedbackType.issueSuccess,
+        Cat((0 until latencyValMaxs(i).get).map { case num =>
+          val latencyNumFuType = fuLatencyMaps(i).get.filter(_._2 == num+1).map(_._1) // futype with latency equal to num+1
+          val isLatencyNum = Cat(latencyNumFuType.map(futype => fuTypeRegVec(OHToUInt(io.deqResp(i).bits.addrOH)) === futype.U)).asUInt().orR() // The latency of the deq inst is Num
+          isLatencyNum
+        }),
+        0.U
+      ) // |  when N cycle is 2 latency, N+1 cycle could not 1 latency
+      val isLNumVecOg0 = WireInit(~(0.U.asTypeOf(isLatencyNumVec)))
+      isLNumVecOg0 := Mux(resps(1)(i).valid && (resps(1)(i).bits.respType === RSFeedbackType.rfArbitFail || resps(1)(i).bits.respType === RSFeedbackType.fuBusy),
+        ~(Cat(Cat((0 until latencyValMaxs(i).get).map { case num =>
+          val latencyNumFuType = fuLatencyMaps(i).get.filter(_._2 == num+1).map(_._1) // futype with latency equal to num+1
+          val isLatencyNum = Cat(latencyNumFuType.map(futype => fuTypeRegVec(OHToUInt(io.og0Resp(i).bits.addrOH)) === futype.U)).asUInt().orR() // The latency of the deq inst is Num
+          isLatencyNum
+        }), 0.U(1.W))),
+        ~(0.U.asTypeOf(isLatencyNumVec))
+        // & ~
+      )
+      val isLNumVecOg1 = WireInit(~(0.U.asTypeOf(isLatencyNumVec)))
+      if(resps.length == 3){
+        isLNumVecOg1 := Mux(resps(2)(i).valid && resps(2)(i).bits.respType === RSFeedbackType.fuBusy,
+          ~(Cat(Cat((0 until latencyValMaxs(i).get).map { case num =>
+            val latencyNumFuType = fuLatencyMaps(i).get.filter(_._2 == num+1).map(_._1) // futype with latency equal to num+1
+            val isLatencyNum = Cat(latencyNumFuType.map(futype => fuTypeRegVec(OHToUInt(io.og1Resp(i).bits.addrOH)) === futype.U)).asUInt().orR() // The latency of the deq inst is Num
+            isLatencyNum
+          }), 0.U(2.W))),
+          ~(0.U.asTypeOf(isLatencyNumVec))
+        )
+        // & ~
+      }
+
+      fuBusyTable(i).get := ((fuBusyTable(i).get << 1.U).asUInt() | isLatencyNumVec) // & isLNumVecOg0.asUInt() & isLNumVecOg1.asUInt()
+    }
+  }
+  // fuBusyTable read
+  for (i <- 0 until params.numDeq){
+    if(fuBusyTable(i).nonEmpty){
+      val isReadLatencyNumVec2 = fuBusyTable(i).get.asBools().reverse.zipWithIndex.map { case (en, idx) =>
+        val isLatencyNumVec = WireInit(0.U(params.numEntries.W))
+        when(en) {
+          isLatencyNumVec := VecInit(fuTypeRegVec.map { case futype =>
+            val latencyNumFuType = fuLatencyMaps(i).get.filter(_._2 == idx).map(_._1)
+            val isLatencyNum = Cat(latencyNumFuType.map(_.U === futype)).asUInt().orR()
+            isLatencyNum
+          }).asUInt()
+        }
+        isLatencyNumVec
+      }
+      if ( latencyValMaxs(i).get > 1 ){
+        fuBusyTableMask(i) := isReadLatencyNumVec2.reduce(_ | _)
+      }else{
+        fuBusyTableMask(i) := isReadLatencyNumVec2.head
+      }
+    } else {
+      fuBusyTableMask(i) := 0.U(params.numEntries.W) // TODO:
+    }
+  }
+
   io.deq.zipWithIndex.foreach { case (deq, i) =>
     deq.valid                := finalDeqSelValidVec(i)
     deq.bits.addrOH          := finalDeqSelOHVec(i)

src/main/scala/xiangshan/backend/issue/Scheduler.scala

@@ -164,9 +164,9 @@ class SchedulerArithImp(override val wrapper: Scheduler)(implicit params: SchdBl
     iq.io.enq <> dispatch2Iq.io.out(i)
     iq.io.wakeup := wakeupFromWBVec
     iq.io.deqResp.zipWithIndex.foreach { case (deqResp, j) =>
-      deqResp.valid := iq.io.deq(j).valid
+      deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready
       deqResp.bits.success := false.B
-      deqResp.bits.respType := Mux(io.toDataPath(i)(j).ready, RSFeedbackType.issueSuccess, RSFeedbackType.fuBusy)
+      deqResp.bits.respType := RSFeedbackType.issueSuccess
       deqResp.bits.addrOH := iq.io.deq(j).bits.addrOH
     }
     iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) =>
@@ -210,9 +210,9 @@ class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBloc
 
   issueQueues.zipWithIndex.foreach { case (iq, i) =>
     iq.io.deqResp.zipWithIndex.foreach { case (deqResp, j) =>
-      deqResp.valid := iq.io.deq(j).valid
+      deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready
       deqResp.bits.success := false.B
-      deqResp.bits.respType := Mux(io.toDataPath(i)(j).ready, RSFeedbackType.issueSuccess, 0.U)
+      deqResp.bits.respType := RSFeedbackType.issueSuccess
       deqResp.bits.addrOH := iq.io.deq(j).bits.addrOH
     }
     iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) =>

src/main/scala/xiangshan/backend/issue/StatusArray.scala

@@ -144,8 +144,6 @@ class StatusArray()(implicit p: Parameters, params: IssueBlockParams) extends XS
         }.elsewhen (RSFeedbackType.isBlocked(deqRespVec(i).bits.respType)) {
           statusNext.issued := false.B
         }
-      }.elsewhen(deqSelVec(i)) {
-        statusNext.issued := true.B
       }
     }
   }