BPU, IFU: Can pass elaborating

src/main/scala/xiangshan/frontend/BPU.scala

@@ -103,7 +103,7 @@ abstract class BPUStage extends XSModule {
     val pred = Decoupled(new BranchPrediction)
     val out = Decoupled(new BPUStageIO)
   }
-  val io = new DefaultIO
+  val io = IO(new DefaultIO)
 
   def npc(pc: UInt, instCount: UInt) = pc + (instCount << 1.U)
 
@@ -265,7 +265,7 @@ class BranchUpdateInfoWithHist extends BranchUpdateInfo {
   val hist = UInt(HistoryLength.W)
 }
 
-abstract class BaseBPU extends XSModule with BranchPredictorComponents{
+abstract class BaseBPU extends XSModule {
   val io = IO(new Bundle() {
     // from backend
     val inOrderBrInfo = Flipped(ValidIO(new BranchUpdateInfoWithHist))
@@ -280,15 +280,25 @@ abstract class BaseBPU extends XSModule with BranchPredictorComponents{
     // to if4, some bpu info used for updating
     val branchInfo = Decoupled(Vec(PredictWidth, new BranchInfo))
   })
+}
+
+
+class FakeBPU extends BaseBPU {
+  io.out.foreach(i => {
+    // Provide not takens
+    i.valid := true.B
+    i.bits <> DontCare
+    i.bits.redirect := false.B
+  })
+  io.branchInfo <> DontCare
+}
+
+class BPU extends BaseBPU {
 
   val s1 = Module(new BPUStage1)
   val s2 = Module(new BPUStage2)
   val s3 = Module(new BPUStage3)
 
-  // TODO: whether to update ubtb when btb successfully 
-  // corrects the wrong prediction from ubtb
-  preds.map(_.io.update <> io.inOrderBrInfo)
-
   s1.io.flush := io.flush(0)
   s2.io.flush := io.flush(1)
   s3.io.flush := io.flush(2)
@@ -300,27 +310,13 @@ abstract class BaseBPU extends XSModule with BranchPredictorComponents{
   io.out(0) <> s1.io.pred
   io.out(1) <> s2.io.pred
   io.out(2) <> s3.io.pred
-  
-  s3.io.predecode <> io.predecode
-
-  io.branchInfo.valid := s3.io.out.valid
-  io.branchInfo.bits := s3.io.out.bits.brInfo
-  s3.io.out.ready := io.branchInfo.ready
-  
-}
-
-
-class FakeBPU extends BaseBPU {
-  io.out.foreach(i => {
-    // Provide not takens
-    i.valid := true.B
-    i.bits := false.B
-  })
-  io.branchInfo <> DontCare
-}
-
-class BPU extends BaseBPU {
 
+  val ubtb = Module(new MicroBTB)
+  val btb = Module(new BTB)
+  val bim = Module(new BIM)
+  val tage = Module(new Tage)
+  val preds = Seq(ubtb, btb, bim, tage)
+  preds.map(_.io.update <> io.inOrderBrInfo)
 
   //**********************Stage 1****************************//
   val s1_fire = s1.io.in.fire()
@@ -373,7 +369,7 @@ class BPU extends BaseBPU {
   s1.io.in.bits.resp := s1_resp_in
   s1.io.in.bits.brInfo <> s1_brInfo_in
 
-
+  //**********************Stage 2****************************//
   tage.io.flush := io.flush(1) // TODO: fix this
   tage.io.pc.valid := s1.io.out.fire()
   tage.io.pc.bits := s1.io.out.bits.pc // PC from s1
@@ -382,12 +378,19 @@ class BPU extends BaseBPU {
   tage.io.s3Fire := s3.io.in.fire() // Tell tage to march 1 stage
   tage.io.bim <> s1.io.out.bits.resp.bim // Use bim results from s1
 
-
+  //**********************Stage 3****************************//
   // Wrap tage response and meta into s3.io.in.bits
   // This is ugly
+  
   s3.io.in.bits.resp.tage <> tage.io.resp
   for (i <- 0 until PredictWidth) {
     s3.io.in.bits.brInfo(i).tageMeta := tage.io.meta(i)
   }
 
+  s3.io.predecode <> io.predecode
+
+  s3.io.out.ready := io.branchInfo.ready
+  
+  io.branchInfo.valid := s3.io.out.valid
+  io.branchInfo.bits := s3.io.out.bits.brInfo
 }

src/main/scala/xiangshan/frontend/Bim.scala

@@ -28,7 +28,7 @@ class BIM extends BasePredictor with BimParams{
     val meta = new BIMMeta
   }
 
-  override val io = new BIMIO
+  override val io = IO(new BIMIO)
   // Update logic
   // 1 calculate new 2-bit saturated counter value
   def satUpdate(old: UInt, len: Int, taken: Bool): UInt = {

src/main/scala/xiangshan/frontend/Btb.scala

@@ -54,7 +54,7 @@ class BTB extends BasePredictor with BTBParams{
     val resp = Output(new BTBResp)
     val meta = Output(new BTBMeta)
   }
-  override val io = new BTBIO
+  override val io = IO(new BTBIO)
   val btbAddr = new TableAddr(log2Up(BtbSize), BtbBanks)
 
   val pcLatch = RegEnable(io.pc.bits, io.pc.valid)

src/main/scala/xiangshan/frontend/IFU.scala

@@ -47,7 +47,7 @@ class IFU extends XSModule with HasIFUConst
   val if2_ready = WireInit(false.B)
   val if1_fire = if1_valid && (if2_ready || if1_flush) && io.icacheReq.ready
 
-  val extHist = RegInit(Vec(ExtHistoryLength, 0.U(1.W)))
+  val extHist = VecInit(Fill(ExtHistoryLength, RegInit(0.U(1.W))))
   val headPtr = RegInit(0.U(log2Up(ExtHistoryLength).W))
   val shiftPtr = WireInit(false.B)
   val newPtr = Wire(UInt(log2Up(ExtHistoryLength).W))
@@ -267,7 +267,7 @@ class IFU extends XSModule with HasIFUConst
   XSDebug("[IF3] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d\n", if3_valid, if3_ready, if3_fire, if3_redirect, if3_flush, if3_pc, if3_histPtr)
   XSDebug("[IF4] v=%d r=%d fire=%d redirect=%d flush=%d pc=%x ptr=%d\n", if4_valid, if4_ready, if4_fire, if4_redirect, if4_flush, if4_pc, if4_histPtr)
 
-  XSDebug("[IF1][icacheReq] v=%d r=%d addr=%x\n", io.icacheReq.valid, io.icacheReq.ready)
+  XSDebug("[IF1][icacheReq] v=%d r=%d addr=%x\n", io.icacheReq.valid, io.icacheReq.ready, io.icacheReq.bits.addr)
   XSDebug("[IF1][ghr] headPtr=%d shiftPtr=%d newPtr=%d ptr=%d\n", headPtr, shiftPtr, newPtr, ptr)
   XSDebug("[IF1][ghr] hist=%b\n", hist.asUInt)
   XSDebug("[IF1][ghr] extHist=%b\n\n", extHist.asUInt)

src/main/scala/xiangshan/frontend/Tage.scala

@@ -274,7 +274,7 @@ class FakeTAGE extends BasePredictor with HasTageParameter {
     val s3Fire = Input(Bool())
   }
 
-  override val io = new TageIO
+  override val io = IO(new TageIO)
 
   io.resp <> DontCare
   io.meta <> DontCare
@@ -297,7 +297,7 @@ class Tage extends BasePredictor with HasTageParameter {
     val s3Fire = Input(Bool())
   }
 
-  override val io = new TageIO
+  override val io = IO(new TageIO)
 
   val tables = TableInfo.map {
     case (nRows, histLen, tagLen) => {

src/test/scala/IFUtest/PDtest.scala

@@ -3,63 +3,63 @@ package IFUtest
 import chisel3._
 import chiseltest._
 import org.scalatest._
-import xiangshan.frontend.PDecode
+import xiangshan.frontend.PreDecode
 
-class PDtest extends FlatSpec with ChiselScalatestTester with Matchers {
-  val cacheLine = ("b" +
-    "100_1_00001_00000_10" +  //rvc jalr
-    "100_0_00001_00000_10" +  //rvc jr
-    "101_00000000000_01" +  //rvc j
-    "001_00000000000_01" +  //rvc jal
-    "111_000_001_00000_01" +  //RVC bnez
-    "110_000_001_00000_01" +  //RVC beqz
-    "0000000_00000_00001_000_10000_1100111" +  //RET
-    "0000000_00000_00101_000_10000_1100111" +  //RET
-    "0000000_00000_00000_000_00101_1100111" +  //JALR_CALL
-    "0000000_00000_00000_000_00001_1100111" +  //JALR_CALL
-    "0000000_00000_00000_000_00101_1101111" +  //JAL_CALL
-    "0000000_00000_00000_000_00001_1101111" +  //JAL_CALL
-    "0000000_00010_00011_000_10000_1100111" +  //JARL
-    "0000000_00000_00000_000_10000_1101111" +  //JAR
-    "0000000_00010_00001_101_00000_1100011" +  //Branch bge
-    "0000000_00010_00001_100_00000_1100011" +  //Branch blt
-    "0000000_00010_00001_001_00000_1100011" +  //Branch bne
-    "0000000_00010_00001_000_00000_1100011" +  //Branch beq
-    "0000000_00010_00001_000_00001_0000011").U //Notbr
-  behavior of "PD Test"
+// class PDtest extends FlatSpec with ChiselScalatestTester with Matchers {
+//   val cacheLine = ("b" +
+//     "100_1_00001_00000_10" +  //rvc jalr
+//     "100_0_00001_00000_10" +  //rvc jr
+//     "101_00000000000_01" +  //rvc j
+//     "001_00000000000_01" +  //rvc jal
+//     "111_000_001_00000_01" +  //RVC bnez
+//     "110_000_001_00000_01" +  //RVC beqz
+//     "0000000_00000_00001_000_10000_1100111" +  //RET
+//     "0000000_00000_00101_000_10000_1100111" +  //RET
+//     "0000000_00000_00000_000_00101_1100111" +  //JALR_CALL
+//     "0000000_00000_00000_000_00001_1100111" +  //JALR_CALL
+//     "0000000_00000_00000_000_00101_1101111" +  //JAL_CALL
+//     "0000000_00000_00000_000_00001_1101111" +  //JAL_CALL
+//     "0000000_00010_00011_000_10000_1100111" +  //JARL
+//     "0000000_00000_00000_000_10000_1101111" +  //JAR
+//     "0000000_00010_00001_101_00000_1100011" +  //Branch bge
+//     "0000000_00010_00001_100_00000_1100011" +  //Branch blt
+//     "0000000_00010_00001_001_00000_1100011" +  //Branch bne
+//     "0000000_00010_00001_000_00000_1100011" +  //Branch beq
+//     "0000000_00010_00001_000_00001_0000011").U //Notbr
+//   behavior of "PD Test"
 
-//  val cacheInst = Wire(Vec(8, UInt(32.W)))
-//
-//  for(i <- 0 until 8) {
-//    cacheInst(i) := cacheLine(i*32+31,i*32)
-//  }
+// //  val cacheInst = Wire(Vec(8, UInt(32.W)))
+// //
+// //  for(i <- 0 until 8) {
+// //    cacheInst(i) := cacheLine(i*32+31,i*32)
+// //  }
 
 
-  it should "test PDecode" in {
-    test(new PDecode) { c =>
-      println(s"\n--------------------cycle 1------------------\n")
-      //c.io.in.valid.poke(true.B)
-      c.io.in(0).poke("b0000000_00010_00001_000_00001_0000011".U)
-      c.io.in(1).poke("b0000000_00010_00001_000_00000_1100011".U)
-      c.io.in(2).poke("b0000000_00010_00001_001_00000_1100011".U)
-      c.io.in(3).poke("b0000000_00010_00001_100_00000_1100011".U)
-      c.io.in(4).poke("b0000000_00010_00001_101_00000_1100011".U)
-      c.io.in(5).poke("b0000000_00000_00000_000_10000_1101111".U)
-      c.io.in(6).poke("b0000000_00010_00011_000_10000_1100111".U)
-      c.io.in(7).poke("b0000000_00000_00000_000_00001_1101111".U)
-      c.clock.step()
-      println(s"\n--------------------cycle 2------------------\n")
-      //c.io.in.valid.poke(true.B)
-      c.io.in(0).poke("b0000000_00010_00001_000_00001_0000011".U)
-      c.io.in(1).poke("b0000000_00010_00001_000_00000_1100011".U)
-      c.io.in(2).poke("b0000000_00010_00001_001_00000_1100011".U)
-      c.io.in(3).poke("b0000000_00010_00001_100_00000_1100011".U)
-      c.io.in(4).poke("b0000000_00010_00001_101_00000_1100011".U)
-      c.io.in(5).poke("b0000000_00000_00000_000_10000_1101111".U)
-      c.io.in(6).poke("b0000000_00010_00011_000_10000_1100111".U)
-      c.io.in(7).poke("b0000000_00000_00000_000_00001_1101111".U)
-      c.clock.step()
-      println(s"\n--------------------cycle 3------------------\n")
-    }
-  }
-}
+//   it should "test PDecode" in {
+//     test(new PDecode) { c =>
+//       println(s"\n--------------------cycle 1------------------\n")
+//       //c.io.in.valid.poke(true.B)
+//       c.io.in(0).poke("b0000000_00010_00001_000_00001_0000011".U)
+//       c.io.in(1).poke("b0000000_00010_00001_000_00000_1100011".U)
+//       c.io.in(2).poke("b0000000_00010_00001_001_00000_1100011".U)
+//       c.io.in(3).poke("b0000000_00010_00001_100_00000_1100011".U)
+//       c.io.in(4).poke("b0000000_00010_00001_101_00000_1100011".U)
+//       c.io.in(5).poke("b0000000_00000_00000_000_10000_1101111".U)
+//       c.io.in(6).poke("b0000000_00010_00011_000_10000_1100111".U)
+//       c.io.in(7).poke("b0000000_00000_00000_000_00001_1101111".U)
+//       c.clock.step()
+//       println(s"\n--------------------cycle 2------------------\n")
+//       //c.io.in.valid.poke(true.B)
+//       c.io.in(0).poke("b0000000_00010_00001_000_00001_0000011".U)
+//       c.io.in(1).poke("b0000000_00010_00001_000_00000_1100011".U)
+//       c.io.in(2).poke("b0000000_00010_00001_001_00000_1100011".U)
+//       c.io.in(3).poke("b0000000_00010_00001_100_00000_1100011".U)
+//       c.io.in(4).poke("b0000000_00010_00001_101_00000_1100011".U)
+//       c.io.in(5).poke("b0000000_00000_00000_000_10000_1101111".U)
+//       c.io.in(6).poke("b0000000_00010_00011_000_10000_1100111".U)
+//       c.io.in(7).poke("b0000000_00000_00000_000_00001_1101111".U)
+//       c.clock.step()
+//       println(s"\n--------------------cycle 3------------------\n")
+//     }
+//   }
+// }

src/test/scala/xiangshan/frontend/PDtest.scala

@@ -33,22 +33,22 @@ class PDtest extends FlatSpec with ChiselScalatestTester with Matchers{
   it should "test PDecode" in {
     test(new PreDecode) { c =>
       println(s"\n--------------------cycle 1------------------\n")
-      c.io.in.fetchPc.poke(0.U)
+      c.io.in.pc.poke(0.U)
       c.io.in.mask.poke("b1111_1111_1111_0000".U)
       c.io.in.data.poke(cacheLine1)
       c.clock.step()
       println(s"\n--------------------cycle 2------------------\n")
-      c.io.in.fetchPc.poke((1<<5).U)
+      c.io.in.pc.poke((1<<5).U)
       c.io.in.mask.poke("b1111_1111_1111_1111".U)
       c.io.in.data.poke(cacheLine2)
       c.clock.step()
       println(s"\n--------------------cycle 3------------------\n")
-      c.io.in.fetchPc.poke((2<<5).U)
+      c.io.in.pc.poke((2<<5).U)
       c.io.in.mask.poke("b1111_1111_1111_1111".U)
       c.io.in.data.poke(cacheLine1)
       c.clock.step()
       println(s"\n--------------------cycle 4------------------\n")
-      c.io.in.fetchPc.poke((3<<5).U)
+      c.io.in.pc.poke((3<<5).U)
       c.io.in.mask.poke("b1111_1111_1111_1111".U)
       c.io.in.data.poke(cacheLine2)
       c.clock.step()