decoder: add rvc call/ret

bpu: fix lastHit in stage3

src/main/scala/xiangshan/backend/decode/DecodeHelper.scala

@@ -56,8 +56,8 @@ object Instructions extends HasInstrType with HasXSParameter {
       Privileged.table ++
       RVFInstr.table ++
       RVDInstr.table ++
-      (if (HasMExtension) RVMInstr.table else Nil) // ++
-//    (if (HasCExtension) RVCInstr.table else Nil) ++
+      (if (HasMExtension) RVMInstr.table else Nil) ++
+      (if (HasCExtension) RVCInstr.table else Nil) // ++
 //    (if (HasFPU) RVFInstr.table ++ RVDInstr.table else Nil) ++
 //    Privileged.table ++
 //    RVAInstr.table ++

src/main/scala/xiangshan/backend/decode/Decoder.scala

@@ -121,10 +121,10 @@ class Decoder extends XSModule with HasInstrType {
 
  when (fuType === FuType.jmp) {
    def isLink(reg: UInt) = (reg === 1.U || reg === 5.U)
-   when (isLink(rd) && fuOpType === JumpOpType.jal) { io.out.ctrl.fuOpType := JumpOpType.call }
+   when (isLink(rfDest) && fuOpType === JumpOpType.jal) { io.out.ctrl.fuOpType := JumpOpType.call }
    when (fuOpType === JumpOpType.jalr) {
-     when (isLink(rs)) { io.out.ctrl.fuOpType := JumpOpType.ret }
-     when (isLink(rd)) { io.out.ctrl.fuOpType := JumpOpType.call }
+     when (isLink(rfSrc1)) { io.out.ctrl.fuOpType := JumpOpType.ret }
+     when (isLink(rfDest)) { io.out.ctrl.fuOpType := JumpOpType.call }
    }
  }
   // fix LUI

src/main/scala/xiangshan/frontend/BPU.scala

@@ -275,7 +275,13 @@ class BPUStage3 extends BPUStage {
   targetSrc := inLatch.resp.btb.targets
 
   lastIsRVC := pds(lastValidPos).isRVC
-  lastHit   := pdMask(lastValidPos)
+  when (lastValidPos > 0.U) {
+    lastHit := pdMask(lastValidPos) |
+      !pdMask(lastValidPos - 1.U) & !pdMask(lastValidPos) |
+      pdMask(lastValidPos - 1.U) & !pdMask(lastValidPos) & pds(lastValidPos - 1.U).isRVC
+  }.otherwise {
+    lastHit := pdMask(0) | !pdMask(0) & !pds(0).isRVC
+  }
 
   // Wrap tage resp and tage meta in
   // This is ugly

src/main/scala/xiangshan/frontend/IFU.scala

@@ -325,7 +325,7 @@ class IFU extends XSModule with HasIFUConst
 
   pd.io.in := io.icacheResp.bits
   pd.io.prev.valid := if3_hasPrevHalfInstr
-  pd.io.prev.bits := prevHalfInstr.target
+  pd.io.prev.bits := prevHalfInstr.instr
 
   io.fetchPacket.valid := if4_valid && !io.redirect.valid
   io.fetchPacket.bits.instrs := if4_pd.instrs

src/main/scala/xiangshan/frontend/PreDecode.scala

@@ -10,9 +10,9 @@ trait HasPdconst{ this: XSModule =>
   def isRVC(inst: UInt) = (inst(1,0) =/= 3.U)
   def isLink(reg:UInt) = reg === 1.U || reg === 5.U
   def brInfo(instr: UInt) = {
-    val rd = instr(11,7)
-    val rs = instr(19,15)
     val brType::Nil = ListLookup(instr, List(BrType.notBr), PreDecodeInst.brTable)
+    val rd = Mux(isRVC(instr), 1.U, instr(11,7))
+    val rs = Mux(isRVC(instr), Mux(brType === BrType.jal, 0.U, instr(11, 7)), instr(19, 15))
     val isCall = (brType === BrType.jal || brType === BrType.jalr) && isLink(rd) && !isRVC(instr)
     val isRet = brType === BrType.jalr && isLink(rs) && !isLink(rd) && !isRVC(instr)
     List(brType, isCall, isRet)