Roq, Lsroq: add replay support

src/main/scala/xiangshan/backend/Backend.scala

@@ -205,6 +205,7 @@ class Backend extends XSModule
   dispatch.io.redirect <> redirect
   dispatch.io.fromRename <> rename.io.out
 
+  roq.io.memRedirect <> io.mem.replayAll
   roq.io.brqRedirect <> brq.io.redirect
   roq.io.dp1Req <> dispatch.io.toRoq
   dispatch.io.roqIdxs <> roq.io.roqIdxs

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -12,6 +12,7 @@ import xiangshan.backend.decode.XSTrap
 class Roq extends XSModule {
   val io = IO(new Bundle() {
     val brqRedirect = Input(Valid(new Redirect))
+    val memRedirect = Input(Valid(new Redirect))
     val dp1Req = Vec(RenameWidth, Flipped(DecoupledIO(new MicroOp)))
     val roqIdxs = Output(Vec(RenameWidth, UInt(RoqIdxWidth.W)))
     val redirect = Output(Valid(new Redirect))
@@ -27,6 +28,7 @@ class Roq extends XSModule {
 
   val microOp = Mem(RoqSize, new MicroOp)
   val valid = RegInit(VecInit(List.fill(RoqSize)(false.B)))
+  val flag = RegInit(VecInit(List.fill(RoqSize)(false.B)))
   val writebacked = Reg(Vec(RoqSize, Bool()))
 
   val exuData = Reg(Vec(RoqSize, UInt(XLEN.W)))//for debug
@@ -57,6 +59,7 @@ class Roq extends XSModule {
     when(io.dp1Req(i).fire()){
       microOp(ringBufferHead+offset) := io.dp1Req(i).bits
       valid(ringBufferHead+offset) := true.B
+      flag(ringBufferHead+offset) := (ringBufferHeadExtended + offset).head(1).asBool()
       writebacked(ringBufferHead+offset) := false.B
       when(csrEnRoq(i)){ hasCsr := true.B }
     }
@@ -227,6 +230,16 @@ class Roq extends XSModule {
     XSDebug("roq full, switched to s_extrawalk. needExtraSpaceForMPR: %b\n", needExtraSpaceForMPR.asUInt)
   }
 
+  // when rollback, reset writebacked entry to valid
+  when(io.brqRedirect.valid && io.brqRedirect.bits.isReplay){ // TODO: opt timing
+    for (i <- 0 until RoqSize) {
+      val recRoqIdx = Cat(flag(i).asUInt, i.U)
+      when(valid(i) && io.memRedirect.bits.isAfter(recRoqIdx)){
+        writebacked(i) := false.B
+      }
+    }
+  }
+
   // when exception occurs, cancels all
   when (io.redirect.valid) {
     ringBufferHeadExtended := 0.U

src/main/scala/xiangshan/mem/pipeline/Lsroq.scala

@@ -92,15 +92,6 @@ class Lsroq extends XSModule {
     XSInfo("dispatched %d insts to moq\n", PopCount(firedDispatch))
   }
 
-  // misprediction recovery / exception redirect
-  // invalidate lsroq term using robIdx
-  // TODO: check exception redirect implementation
-  (0 until MoqSize).map(i => {
-    when(uop(i).needFlush(io.brqRedirect) && allocated(i) && !commited(i)) {
-      allocated(i) := false.B
-    }
-  })
-
   // writeback load
   (0 until LoadPipelineWidth).map(i => {
     assert(!io.loadIn(i).bits.miss)
@@ -506,6 +497,23 @@ class Lsroq extends XSModule {
 
   io.rollback := ParallelOperation(rollback, rollbackSel)
 
+  // misprediction recovery / exception redirect
+  // invalidate lsroq term using robIdx
+  // TODO: check exception redirect implementation
+  (0 until MoqSize).map(i => {
+    when(uop(i).needFlush(io.brqRedirect) && allocated(i) && !commited(i)) {
+      when(io.brqRedirect.bits.isReplay){
+        valid(i) := false.B
+        store(i) := false.B
+        writebacked(i) := false.B
+        listening(i) := false.B
+        miss(i) := false.B
+      }.otherwise{
+        allocated(i) := false.B
+      }
+    }
+  })
+
   // assert(!io.rollback.valid)
   when(io.rollback.valid) {
     XSDebug("Mem rollback: pc %x roqidx %d\n", io.rollback.bits.pc, io.rollback.bits.roqIdx)