L2Prefetcher/L1plusPrefetcher: add perf cnt for prefetch penalty

src/main/scala/xiangshan/backend/fu/CSR.scala

@@ -833,7 +833,9 @@ class CSR extends FunctionUnit with HasCSRConst
     "PtwL2TlbHit" -> (0xb27, "perfCntPtwL2TlbHit"     ),
     "ICacheReq"   -> (0xb28, "perfCntIcacheReqCnt"     ),
     "ICacheMiss"   -> (0xb29, "perfCntIcacheMissCnt"     ),
-    "DCacheMiss"  -> (0xb2a, "perfCntDCacheMiss"      )
+    "DCacheMiss"  -> (0xb2a, "perfCntDCacheMiss"      ),
+    "L1+PrefetchCnt"->(0xb2b, "perfCntL1plusPrefetchReqCnt"),
+    "L2PrefetchCnt"->(0xb2c, "perfCntL2PrefetchReqCnt")
     // "FetchFromICache" -> (0xb2a, "CntFetchFromICache"),
     // "FetchFromLoopBuffer" -> (0xb2b, "CntFetchFromLoopBuffer"),
     // "ExitLoop1" -> (0xb2c, "CntExitLoop1"),
@@ -850,11 +852,19 @@ class CSR extends FunctionUnit with HasCSRConst
 //    "Ml2cacheHit" -> (0xb23, "perfCntCondMl2cacheHit")
   ) ++ (
     (0 until dcacheParameters.nMissEntries).map(i => 
-      ("DCacheMissQueuePenalty" + Integer.toString(i, 10), (0xb2b + i, "perfCntDCacheMissQueuePenaltyEntry" + Integer.toString(i, 10)))
+      ("DCacheMissQueuePenalty" + Integer.toString(i, 10), (0xb2d + i, "perfCntDCacheMissQueuePenaltyEntry" + Integer.toString(i, 10)))
     ).toMap
   ) ++ (
     (0 until icacheParameters.nMissEntries).map(i =>
-      ("ICacheMissQueuePenalty" + Integer.toString(i, 10), (0xb2b + dcacheParameters.nMissEntries + i, "perfCntICacheMissQueuePenalty" + Integer.toString(i, 10)))
+      ("ICacheMissQueuePenalty" + Integer.toString(i, 10), (0xb2d + dcacheParameters.nMissEntries + i, "perfCntICacheMissQueuePenaltyEntry" + Integer.toString(i, 10)))
+    ).toMap
+  ) ++ (
+    (0 until l1plusPrefetcherParameters.nEntries).map(i =>
+      ("L1+PrefetchPenalty" + Integer.toString(i, 10), (0xb2d + dcacheParameters.nMissEntries + icacheParameters.nMissEntries, "perfCntL1plusPrefetchPenaltyEntry" + Integer.toString(i, 10)))
+    ).toMap
+  ) ++ (
+    (0 until l2PrefetcherParameters.nEntries).map(i =>
+      ("L2PrefetchPenalty" + Integer.toString(i, 10), (0xb2d + dcacheParameters.nMissEntries + icacheParameters.nMissEntries + l1plusPrefetcherParameters.nEntries, "perfCntL2PrefetchPenaltyEntry" + Integer.toString(i, 10)))
     ).toMap
   )
 

src/main/scala/xiangshan/cache/icacheMissQueue.scala

@@ -233,7 +233,7 @@ class IcacheMissQueue extends ICacheMissQueueModule
       ExcitingUtils.addSource(
         BoolStopWatch(
           start = entry.io.req.fire(),
-          stop = entry.io.resp.fire(),
+          stop = entry.io.resp.fire() || entry.io.flush,
           startHighPriority = true),
         "perfCntICacheMissQueuePenaltyEntry" + Integer.toString(i, 10),
         Perf

src/main/scala/xiangshan/cache/prefetch/L1plusPrefetcher.scala

@@ -5,6 +5,7 @@ import chisel3.util._
 import xiangshan._
 import xiangshan.cache._
 import utils._
+import chisel3.ExcitingUtils._
 
 case class L1plusPrefetcherParameters(
   enable: Boolean,
@@ -49,6 +50,22 @@ class L1plusPrefetcher extends PrefetchModule {
     XSDebug(p"io.mem_acquire: v=${io.mem_acquire.valid} r=${io.mem_acquire.ready} ${io.mem_acquire.bits}\n")
     XSDebug(p"io.mem_grant:   v=${io.mem_grant.valid} r=${io.mem_grant.ready} ${io.mem_grant.bits}\n")
 
+    if (!env.FPGAPlatform) {
+      ExcitingUtils.addSource(io.mem_acquire.fire(), "perfCntL1plusPrefetchReqCnt", Perf)
+      def idWidth: Int = log2Up(l1plusPrefetcherParameters.nEntries)
+      (0 until l1plusPrefetcherParameters.nEntries).foreach(i =>
+        ExcitingUtils.addSource(
+          BoolStopWatch(
+            start = io.mem_acquire.fire() && io.mem_acquire.bits.id(idWidth - 1, 0) === i.U,
+            stop = io.mem_grant.fire() && io.mem_grant.bits.id(idWidth - 1, 0) === i.U,
+            startHighPriority = true
+          ),
+          "perfCntL1plusPrefetchPenaltyEntry" + Integer.toString(i, 10),
+          Perf
+        )
+      )
+    }
+
   } else {
     io.in.ready := true.B
     io.mem_acquire.valid := false.B

src/main/scala/xiangshan/cache/prefetch/L2Prefetcher.scala

@@ -6,6 +6,7 @@ import freechips.rocketchip.tilelink.ClientMetadata
 import xiangshan._
 import xiangshan.cache._
 import utils._
+import chisel3.ExcitingUtils._
 
 import chipsalliance.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, IdRange}
@@ -79,6 +80,22 @@ class L2PrefetcherImp(outer: L2Prefetcher) extends LazyModuleImp(outer) with Has
     bus.e.bits := DontCare
     dPrefetch.io.finish.ready := true.B
 
+    if (!env.FPGAPlatform) {
+      ExcitingUtils.addSource(bus.a.fire(), "perfCntL2PrefetchReqCnt", Perf)
+      def idWidth = log2Up(l2PrefetcherParameters.nEntries)
+      (0 until l2PrefetcherParameters.nEntries).foreach(i =>
+        ExcitingUtils.addSource(
+          BoolStopWatch(
+            start = bus.a.fire() && dPrefetch.io.req.bits.id(streamParams.totalWidth - 1, 0) === i.U,
+            stop = bus.d.fire() && bus.d.bits.source(streamParams.totalWidth - 1, 0) === i.U,
+            startHighPriority = true
+          ),
+          "perfCntL2PrefetchPenaltyEntry" + Integer.toString(i, 10),
+          Perf
+        )
+      )
+    }
+
   } else {
     bus.a.valid := false.B
     bus.a.bits := DontCare