提交 e545d9cd 编写于 作者: W William Wang

Roq: opt roq enq logic [WIP]

上级 43ed2475
......@@ -72,6 +72,7 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
// uop.ctrl.commitType (wb) (commit) (L/S)
// exceptionVec (wb) (commit)
// roqIdx (dispatch) (commit)
// crossPageIPFFix (dispatch) (commit)
// uop field used when walk
// ctrl.fpWen (dispatch) (walk)
......@@ -95,6 +96,8 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
val isFull = enqPtr === deqPtr && enqPtrExt.flag =/= deqPtrExt.flag
val notFull = !isFull
val emptyEntries = RoqSize.U - distanceBetween(enqPtrExt, deqPtrExt)
val s_idle :: s_walk :: s_extrawalk :: Nil = Enum(3)
val state = RegInit(s_idle)
......@@ -131,7 +134,9 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
debug_microOp(roqIdx) := io.dp1Req(i).bits
when(noSpecEnq(i)){ hasNoSpec := true.B }
}
io.dp1Req(i).ready := (notFull && !valid(roqIdx) && state === s_idle) &&
val numTryEnqueue = offset +& io.dp1Req(i).valid
io.dp1Req(i).ready := numTryEnqueue <= emptyEntries &&
state === s_idle &&
(!noSpecEnq(i) || isEmpty) &&
!hasNoSpec
io.roqIdxs(i) := roqIdxExt
......
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