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体验新版 GitCode,发现更多精彩内容 >>
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e4beff2a
编写于
12月 13, 2020
作者:
Y
Yinan Xu
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电子邮件补丁
差异文件
freelist: generate 6 pdests first and then select from them
上级
be3a8936
变更
1
隐藏空白更改
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1 changed file
with
5 addition
and
8 deletion
+5
-8
src/main/scala/xiangshan/backend/rename/FreeList.scala
src/main/scala/xiangshan/backend/rename/FreeList.scala
+5
-8
未找到文件。
src/main/scala/xiangshan/backend/rename/FreeList.scala
浏览文件 @
e4beff2a
...
@@ -84,22 +84,19 @@ class FreeList extends XSModule with HasFreeListConsts with HasCircularQueuePtrH
...
@@ -84,22 +84,19 @@ class FreeList extends XSModule with HasFreeListConsts with HasCircularQueuePtrH
io
.
req
.
canAlloc
:=
RegNext
(
freeRegs
>=
RenameWidth
.
U
)
io
.
req
.
canAlloc
:=
RegNext
(
freeRegs
>=
RenameWidth
.
U
)
XSDebug
(
p
"free regs: $freeRegs\n"
)
XSDebug
(
p
"free regs: $freeRegs\n"
)
val
allocatePtrs
=
(
0
until
RenameWidth
).
map
(
i
=>
headPtr
+
i
.
U
)
val
newHeadPtrs
=
((
0
until
RenameWidth
)
map
{
i
=>
val
allocatePdests
=
VecInit
(
allocatePtrs
.
map
(
ptr
=>
freeList
(
ptr
.
value
)))
if
(
i
==
0
)
headPtr
else
headPtr
+
PopCount
(
io
.
req
.
allocReqs
.
take
(
i
))
})
:+
(
headPtr
+
PopCount
(
io
.
req
.
allocReqs
))
for
(
i
<-
0
until
RenameWidth
){
for
(
i
<-
0
until
RenameWidth
){
val
ptr
=
newHeadPtrs
(
i
)
io
.
req
.
pdests
(
i
)
:=
allocatePdests
(
/*if (i == 0) 0.U else */
PopCount
(
io
.
req
.
allocReqs
.
take
(
i
)))
val
idx
=
ptr
.
value
io
.
req
.
pdests
(
i
)
:=
freeList
(
idx
)
// when(io.cpReqs(i).valid){
// when(io.cpReqs(i).valid){
// checkPoints(io.cpReqs(i).bits.value) := newHeadPtrs(i+1)
// checkPoints(io.cpReqs(i).bits.value) := newHeadPtrs(i+1)
// XSDebug(p"do checkPt at BrqIdx=${io.cpReqs(i).bits.value} ${newHeadPtrs(i+1)}\n")
// XSDebug(p"do checkPt at BrqIdx=${io.cpReqs(i).bits.value} ${newHeadPtrs(i+1)}\n")
// }
// }
XSDebug
(
p
"req:${io.req.allocReqs(i)} canAlloc:${io.req.canAlloc} pdest:${io.req.pdests(i)}\n"
)
XSDebug
(
p
"req:${io.req.allocReqs(i)} canAlloc:${io.req.canAlloc} pdest:${io.req.pdests(i)}\n"
)
}
}
val
headPtrNext
=
Mux
(
io
.
req
.
canAlloc
&&
io
.
req
.
doAlloc
,
newHeadPtrs
.
last
,
headPtr
)
val
headPtrAllocate
=
headPtr
+
PopCount
(
io
.
req
.
allocReqs
)
val
headPtrNext
=
Mux
(
io
.
req
.
canAlloc
&&
io
.
req
.
doAlloc
,
headPtrAllocate
,
headPtr
)
freeRegs
:=
distanceBetween
(
tailPtr
,
headPtrNext
)
freeRegs
:=
distanceBetween
(
tailPtr
,
headPtrNext
)
// when mispredict or exception happens, reset headPtr to tailPtr (freelist is full).
// when mispredict or exception happens, reset headPtr to tailPtr (freelist is full).
...
...
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