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e3c64101
编写于
11月 20, 2020
作者:
Y
Yinan Xu
浏览文件
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浏览文件
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差异文件
Merge branch 'fix-module-level' of github.com:RISCVERS/XiangShan into fix-module-level
上级
b36e97e2
a1c2ca77
变更
3
展开全部
隐藏空白更改
内联
并排
Showing
3 changed file
with
686 addition
and
16 deletion
+686
-16
Makefile
Makefile
+9
-5
src/main/resources/vsrc/regfile_160x64_10w16r_sim.v
src/main/resources/vsrc/regfile_160x64_10w16r_sim.v
+558
-0
src/main/scala/xiangshan/backend/regfile/Regfile.scala
src/main/scala/xiangshan/backend/regfile/Regfile.scala
+119
-11
未找到文件。
Makefile
浏览文件 @
e3c64101
...
...
@@ -59,12 +59,19 @@ EMU_CXXFLAGS += -std=c++11 -static -Wall -I$(EMU_CSRC_DIR)
EMU_CXXFLAGS
+=
-DVERILATOR
-Wno-maybe-uninitialized
EMU_LDFLAGS
=
-lpthread
-lSDL2
-ldl
VEXTRA_FLAGS
=
-I
$(
abspath
$(BUILD_DIR)
)
--x-assign
unique
-O3
-CFLAGS
"
$(EMU_CXXFLAGS)
"
-LDFLAGS
"
$(EMU_LDFLAGS)
"
# Verilator trace support
VEXTRA_FLAGS
=
--trace
EMU_TRACE
?=
0
ifeq
($(EMU_TRACE),1)
VEXTRA_FLAGS
+=
--trace
endif
# Verilator multi-thread support
EMU_THREADS
?=
1
ifneq
($(EMU_THREADS),1)
VEXTRA_FLAGS
+=
--threads
$(EMU_THREADS)
--threads-dpi
none
endif
# Verilator savable
EMU_SNAPSHOT
?=
0
...
...
@@ -83,10 +90,7 @@ VERILATOR_FLAGS = --top-module $(SIM_TOP) \
--assert
\
--stats-vars
\
--output-split
5000
\
--output-split-cfuncs
5000
\
-I
$(
abspath
$(BUILD_DIR)
)
\
--x-assign
unique
-O3
-CFLAGS
"
$(EMU_CXXFLAGS)
"
\
-LDFLAGS
"
$(EMU_LDFLAGS)
"
--output-split-cfuncs
5000
EMU_MK
:=
$(BUILD_DIR)
/emu-compile/V
$(SIM_TOP)
.mk
EMU_DEPS
:=
$(EMU_VFILES)
$(EMU_CXXFILES)
...
...
src/main/resources/vsrc/regfile_160x64_10w16r_sim.v
0 → 100755
浏览文件 @
e3c64101
此差异已折叠。
点击以展开。
src/main/scala/xiangshan/backend/regfile/Regfile.scala
浏览文件 @
e3c64101
...
...
@@ -27,20 +27,24 @@ class Regfile
val
writePorts
=
Vec
(
numWirtePorts
,
new
RfWritePort
)
})
val
mem
=
Mem
(
NRPhyRegs
,
UInt
(
len
.
W
))
for
(
r
<-
io
.
readPorts
){
val
addr_reg
=
RegNext
(
r
.
addr
)
r
.
data
:=
{
if
(
hasZero
)
Mux
(
addr_reg
===
0.
U
,
0.
U
,
mem
(
addr_reg
))
else
mem
(
addr_reg
)}
}
for
(
w
<-
io
.
writePorts
){
when
(
w
.
wen
){
mem
(
w
.
addr
)
:=
w
.
data
}
}
if
(!
env
.
FPGAPlatform
)
{
val
mem
=
Mem
(
NRPhyRegs
,
UInt
(
len
.
W
))
for
(
r
<-
io
.
readPorts
){
val
addr_reg
=
RegNext
(
r
.
addr
)
r
.
data
:=
{
if
(
hasZero
)
Mux
(
addr_reg
===
0.
U
,
0.
U
,
mem
(
addr_reg
))
else
mem
(
addr_reg
)}
}
for
(
w
<-
io
.
writePorts
){
when
(
w
.
wen
){
mem
(
w
.
addr
)
:=
w
.
data
}
}
val
debugArchRat
=
WireInit
(
VecInit
(
Seq
.
fill
(
32
)(
0.
U
(
PhyRegIdxWidth
.
W
))))
ExcitingUtils
.
addSink
(
debugArchRat
,
...
...
@@ -56,6 +60,110 @@ class Regfile
if
(
hasZero
)
"DEBUG_INT_ARCH_REG"
else
"DEBUG_FP_ARCH_REG"
,
ExcitingUtils
.
Debug
)
}
else
{
val
regfile
=
Module
(
new
RegfileBlackBox
)
regfile
.
io
.
clk
:=
this
.
clock
regfile
.
io
.
gpr
:=
hasZero
.
B
regfile
.
io
.
wen0
:=
io
.
writePorts
(
0
).
wen
regfile
.
io
.
waddr0
:=
io
.
writePorts
(
0
).
addr
regfile
.
io
.
wdata0
:=
io
.
writePorts
(
0
).
data
regfile
.
io
.
wen1
:=
io
.
writePorts
(
1
).
wen
regfile
.
io
.
waddr1
:=
io
.
writePorts
(
1
).
addr
regfile
.
io
.
wdata1
:=
io
.
writePorts
(
1
).
data
regfile
.
io
.
wen2
:=
io
.
writePorts
(
2
).
wen
regfile
.
io
.
waddr2
:=
io
.
writePorts
(
2
).
addr
regfile
.
io
.
wdata2
:=
io
.
writePorts
(
2
).
data
regfile
.
io
.
wen3
:=
io
.
writePorts
(
3
).
wen
regfile
.
io
.
waddr3
:=
io
.
writePorts
(
3
).
addr
regfile
.
io
.
wdata3
:=
io
.
writePorts
(
3
).
data
regfile
.
io
.
wen4
:=
io
.
writePorts
(
4
).
wen
regfile
.
io
.
waddr4
:=
io
.
writePorts
(
4
).
addr
regfile
.
io
.
wdata4
:=
io
.
writePorts
(
4
).
data
regfile
.
io
.
wen5
:=
io
.
writePorts
(
5
).
wen
regfile
.
io
.
waddr5
:=
io
.
writePorts
(
5
).
addr
regfile
.
io
.
wdata5
:=
io
.
writePorts
(
5
).
data
regfile
.
io
.
wen6
:=
io
.
writePorts
(
6
).
wen
regfile
.
io
.
waddr6
:=
io
.
writePorts
(
6
).
addr
regfile
.
io
.
wdata6
:=
io
.
writePorts
(
6
).
data
regfile
.
io
.
wen7
:=
io
.
writePorts
(
7
).
wen
regfile
.
io
.
waddr7
:=
io
.
writePorts
(
7
).
addr
regfile
.
io
.
wdata7
:=
io
.
writePorts
(
7
).
data
regfile
.
io
.
wen8
:=
false
.
B
//io.writePorts(8).wen
regfile
.
io
.
waddr8
:=
DontCare
//io.writePorts(8).addr
regfile
.
io
.
wdata8
:=
DontCare
//io.writePorts(8).data
regfile
.
io
.
wen9
:=
false
.
B
//io.writePorts(9).wen
regfile
.
io
.
waddr9
:=
DontCare
//io.writePorts(9).addr
regfile
.
io
.
wdata9
:=
DontCare
//io.writePorts(9).data
regfile
.
io
.
raddr0
:=
io
.
readPorts
(
0
).
addr
regfile
.
io
.
raddr1
:=
io
.
readPorts
(
1
).
addr
regfile
.
io
.
raddr2
:=
io
.
readPorts
(
2
).
addr
regfile
.
io
.
raddr3
:=
io
.
readPorts
(
3
).
addr
regfile
.
io
.
raddr4
:=
io
.
readPorts
(
4
).
addr
regfile
.
io
.
raddr5
:=
io
.
readPorts
(
5
).
addr
regfile
.
io
.
raddr6
:=
io
.
readPorts
(
6
).
addr
regfile
.
io
.
raddr7
:=
io
.
readPorts
(
7
).
addr
regfile
.
io
.
raddr8
:=
io
.
readPorts
(
8
).
addr
regfile
.
io
.
raddr9
:=
io
.
readPorts
(
9
).
addr
regfile
.
io
.
raddr10
:=
io
.
readPorts
(
10
).
addr
regfile
.
io
.
raddr11
:=
io
.
readPorts
(
11
).
addr
regfile
.
io
.
raddr12
:=
io
.
readPorts
(
12
).
addr
regfile
.
io
.
raddr13
:=
io
.
readPorts
(
13
).
addr
regfile
.
io
.
raddr14
:=
DontCare
//io.readPorts(14).addr
regfile
.
io
.
raddr15
:=
DontCare
//io.readPorts(15).addr
io
.
readPorts
(
0
).
data
:=
regfile
.
io
.
rdata0
io
.
readPorts
(
1
).
data
:=
regfile
.
io
.
rdata1
io
.
readPorts
(
2
).
data
:=
regfile
.
io
.
rdata2
io
.
readPorts
(
3
).
data
:=
regfile
.
io
.
rdata3
io
.
readPorts
(
4
).
data
:=
regfile
.
io
.
rdata4
io
.
readPorts
(
5
).
data
:=
regfile
.
io
.
rdata5
io
.
readPorts
(
6
).
data
:=
regfile
.
io
.
rdata6
io
.
readPorts
(
7
).
data
:=
regfile
.
io
.
rdata7
io
.
readPorts
(
8
).
data
:=
regfile
.
io
.
rdata8
io
.
readPorts
(
9
).
data
:=
regfile
.
io
.
rdata9
io
.
readPorts
(
10
).
data
:=
regfile
.
io
.
rdata10
io
.
readPorts
(
11
).
data
:=
regfile
.
io
.
rdata11
io
.
readPorts
(
12
).
data
:=
regfile
.
io
.
rdata12
io
.
readPorts
(
13
).
data
:=
regfile
.
io
.
rdata13
}
}
class
RegfileBlackBox
extends
BlackBox
with
HasBlackBoxResource
{
val
io
=
IO
(
new
Bundle
{
val
clk
=
Input
(
Clock
())
val
gpr
=
Input
(
Bool
())
// write
val
wen0
,
wen1
,
wen2
,
wen3
,
wen4
,
wen5
,
wen6
,
wen7
,
wen8
,
wen9
=
Input
(
Bool
())
val
waddr0
,
waddr1
,
waddr2
,
waddr3
,
waddr4
,
waddr5
,
waddr6
,
waddr7
,
waddr8
,
waddr9
=
Input
(
UInt
(
8.
W
))
val
wdata0
,
wdata1
,
wdata2
,
wdata3
,
wdata4
,
wdata5
,
wdata6
,
wdata7
,
wdata8
,
wdata9
=
Input
(
UInt
(
64.
W
))
// read
val
raddr0
,
raddr1
,
raddr2
,
raddr3
,
raddr4
,
raddr5
,
raddr6
,
raddr7
=
Input
(
UInt
(
8.
W
))
val
raddr8
,
raddr9
,
raddr10
,
raddr11
,
raddr12
,
raddr13
,
raddr14
,
raddr15
=
Input
(
UInt
(
8.
W
))
val
rdata0
,
rdata1
,
rdata2
,
rdata3
,
rdata4
,
rdata5
,
rdata6
,
rdata7
=
Output
(
UInt
(
64.
W
))
val
rdata8
,
rdata9
,
rdata10
,
rdata11
,
rdata12
,
rdata13
,
rdata14
,
rdata15
=
Output
(
UInt
(
64.
W
))
})
val
vsrc
=
"/vsrc/regfile_160x64_10w16r_sim.v"
println
(
s
"Regfile: Using verilog source at: $vsrc"
)
setResource
(
vsrc
)
}
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