decode: support ecall

src/main/scala/xiangshan/backend/decode/DecodeHelper.scala

@@ -52,6 +52,7 @@ object Instructions extends HasInstrType with HasXSParameter {
     RVIInstr.table ++
       XSTrap.table ++
       RVZicsrInstr.table ++
+      RVZifenceiInstr.table ++
       Privileged.table ++
       RVFInstr.table ++
       RVDInstr.table ++
@@ -60,7 +61,7 @@ object Instructions extends HasInstrType with HasXSParameter {
 //    (if (HasFPU) RVFInstr.table ++ RVDInstr.table else Nil) ++
 //    Privileged.table ++
 //    RVAInstr.table ++
-//    RVZicsrInstr.table ++ RVZifenceiInstr.table
+//    RVZicsrInstr.table
 }
 
 object CInstructions extends HasInstrType with HasXSParameter {

src/main/scala/xiangshan/backend/decode/isa/RVZifencei.scala

@@ -3,12 +3,16 @@ package xiangshan.backend.decode.isa
 import chisel3._
 import chisel3.util._
 import xiangshan.FuType
+import xiangshan.backend.ALUOpType
 import xiangshan.backend.decode._
+import xiangshan.backend.decode.isa.RV64IInstr.InstrI
 
 
 object RVZifenceiInstr extends HasInstrType {
   def FENCEI = BitPat("b000000000000_00000_001_00000_0001111")
 
   // fixme: add rvzifencei inst
-  val table = Array()
+  val table = Array(
+    FENCEI -> List(InstrI, FuType.alu, ALUOpType.add)
+  )
 }

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -217,7 +217,7 @@ class Roq(implicit val p: XSConfig) extends XSModule {
   io.redirect.bits.target := trapTarget
   io.exception := microOp(ringBufferTail)
 
-  XSDebug(io.redirect.valid, "generate exception: pc 0x%x target 0x%x\n", io.exception.cf.pc, trapTarget)
+  XSDebug(io.redirect.valid, "generate exception: pc 0x%x target 0x%x exceptionVec %b\n", io.exception.cf.pc, trapTarget, Cat(microOp(ringBufferTail).cf.exceptionVec))
 
   // debug info
   XSDebug("head %d:%d tail %d:%d\n", ringBufferHeadExtended(InnerRoqIdxWidth), ringBufferHead, ringBufferTailExtended(InnerRoqIdxWidth), ringBufferTail)