提交 e1e9dcfa 编写于 作者: L LinJiawei

Add cache ctrl node

上级 d200f594
Subproject commit cc8234aa96c01337bfc60632968e67b26a8071ef
Subproject commit c8f20742a9ce3d2b9496db0d932094d1f07e3600
......@@ -244,7 +244,10 @@ class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1
val l2params = core.L2CacheParamsOpt.get.toCacheParams
l2params.copy(sets = 2 * l2params.sets, ways = l2params.ways)
},
enablePerf = true
enablePerf = true,
ctrl = Some(CacheCtrl(
address = 0x39000000
))
))
)
})
......
......@@ -90,6 +90,10 @@ class XSTop()(implicit p: Parameters) extends BaseXSSoc() with HasSoCParameter
})))
)
if(l3cacheOpt.nonEmpty && l3cacheOpt.get.ctlnode.nonEmpty){
l3cacheOpt.get.ctlnode.get := misc.peripheralXbar
}
l3cacheOpt match {
case Some(l3) =>
misc.l3_out :*= l3.node :*= misc.l3_banked_xbar
......
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