dispatch2: don't allow dequeue when one of rs is not ready

src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala

@@ -20,45 +20,24 @@ class Dispatch2Fp extends XSModule {
   /**
     * Part 1: generate indexes for reservation stations
     */
-  assert(exuParameters.JmpCnt == 1)
   val fmacIndexGen = Module(new IndexMapping(dpParams.FpDqDeqWidth, exuParameters.FmacCnt, true))
-  val fmiscIndexGen = Module(new IndexMapping(dpParams.FpDqDeqWidth, exuParameters.FmiscCnt, true))
+  val fmacCanAccept = VecInit(io.fromDq.map(deq => deq.valid && fmacExeUnitCfg.canAccept(deq.bits.ctrl.fuType)))
   val fmacPriority = PriorityGen((0 until exuParameters.FmacCnt).map(i => io.numExist(i)))
+  fmacIndexGen.io.validBits := fmacCanAccept
+  fmacIndexGen.io.priority := fmacPriority
+
+  val fmiscIndexGen = Module(new IndexMapping(dpParams.FpDqDeqWidth, exuParameters.FmiscCnt, true))
+  val fmiscCanAccept = VecInit(io.fromDq.map(deq => deq.valid && fmiscExeUnitCfg.canAccept(deq.bits.ctrl.fuType)))
   val fmiscPriority = PriorityGen((0 until exuParameters.FmiscCnt).map(i => io.numExist(i+exuParameters.FmacCnt)))
-  for (i <- 0 until dpParams.FpDqDeqWidth) {
-    fmacIndexGen.io.validBits(i) := io.fromDq(i).valid && fmacExeUnitCfg.canAccept(io.fromDq(i).bits.ctrl.fuType)
-    fmiscIndexGen.io.validBits(i) := io.fromDq(i).valid && fmiscExeUnitCfg.canAccept(io.fromDq(i).bits.ctrl.fuType)
+  fmiscIndexGen.io.validBits := fmiscCanAccept
+  fmiscIndexGen.io.priority := fmiscPriority
 
-    // XSDebug(io.fromDq(i).valid,
-    //   p"fp dp queue $i: ${Hexadecimal(io.fromDq(i).bits.cf.pc)} type ${Binary(io.fromDq(i).bits.ctrl.fuType)}\n")
-  }
-  for (i <- 0 until exuParameters.FmacCnt) {
-    fmacIndexGen.io.priority(i) := fmacPriority(i)
-  }
-  for (i <- 0 until exuParameters.FmiscCnt) {
-    fmiscIndexGen.io.priority(i) := fmiscPriority(i)
-  }
   val allIndexGen = Seq(fmacIndexGen, fmiscIndexGen)
   val validVec = allIndexGen.map(_.io.mapping.map(_.valid)).reduceLeft(_ ++ _)
   val indexVec = allIndexGen.map(_.io.mapping.map(_.bits)).reduceLeft(_ ++ _)
-  val rsValidVec = (0 until dpParams.FpDqDeqWidth).map(i => Cat(allIndexGen.map(_.io.reverseMapping(i).valid)).orR())
-  val rsIndexVec = (0 until dpParams.FpDqDeqWidth).map({i =>
-    val indexOffset = Seq(0, exuParameters.FmacCnt)
-    allIndexGen.zipWithIndex.map{
-      case (index, j) => Mux(index.io.reverseMapping(i).valid,
-        ZeroExt(index.io.reverseMapping(i).bits, log2Ceil(exuParameters.FpExuCnt)) + indexOffset(j).U,
-        0.U)
-    }.reduce(_ | _)
-  })
-
   for (i <- validVec.indices) {
     // XSDebug(p"mapping $i: valid ${validVec(i)} index ${indexVec(i)}\n")
   }
-  for (i <- rsValidVec.indices) {
-    // XSDebug(p"fmac reverse $i: valid ${fmacIndexGen.io.reverseMapping(i).valid} index ${fmacIndexGen.io.reverseMapping(i).bits}\n")
-    // XSDebug(p"fmisc reverse $i: valid ${fmiscIndexGen.io.reverseMapping(i).valid} index ${fmiscIndexGen.io.reverseMapping(i).bits}\n")
-    // XSDebug(p"reverseMapping $i: valid ${rsValidVec(i)} index ${rsIndexVec(i)}\n")
-  }
 
   /**
     * Part 2: assign regfile read ports
@@ -83,9 +62,16 @@ class Dispatch2Fp extends XSModule {
   /**
     * Part 3: dispatch to reservation stations
     */
+  val fmacReady = Cat(io.enqIQCtrl.take(exuParameters.FmacCnt).map(_.ready)).andR
+  val fmiscReady = Cat(io.enqIQCtrl.drop(exuParameters.FmacCnt).map(_.ready)).andR
   for (i <- 0 until exuParameters.FpExuCnt) {
     val enq = io.enqIQCtrl(i)
-    enq.valid := validVec(i)
+    if (i < exuParameters.FmacCnt) {
+      enq.valid := fmacIndexGen.io.mapping(i).valid && fmacReady
+    }
+    else {
+      enq.valid := fmiscIndexGen.io.mapping(i - exuParameters.FmacCnt).valid && fmiscReady
+    }
     enq.bits := io.fromDq(indexVec(i)).bits
     enq.bits.src1State := io.regRdy(readPortIndex(i))
     enq.bits.src2State := io.regRdy(readPortIndex(i) + 1.U)
@@ -99,14 +85,18 @@ class Dispatch2Fp extends XSModule {
   /**
     * Part 4: response to dispatch queue
     */
+  val fmisc2CanOut = !(fmiscCanAccept(0) && fmiscCanAccept(1))
+  val fmisc3CanOut = !(fmiscCanAccept(0) && fmiscCanAccept(1) || fmiscCanAccept(0) && fmiscCanAccept(2) || fmiscCanAccept(1) && fmiscCanAccept(2))
   for (i <- 0 until dpParams.FpDqDeqWidth) {
-    io.fromDq(i).ready := rsValidVec(i) && io.enqIQCtrl(rsIndexVec(i)).ready
+    io.fromDq(i).ready := fmacCanAccept(i) && fmacReady ||
+                          fmiscCanAccept(i) && (if (i <= 1) true.B else if (i == 2) fmisc2CanOut else fmisc3CanOut) && fmiscReady
 
     XSInfo(io.fromDq(i).fire(),
       p"pc 0x${Hexadecimal(io.fromDq(i).bits.cf.pc)} leaves Fp dispatch queue $i with nroq ${io.fromDq(i).bits.roqIdx}\n")
     XSDebug(io.fromDq(i).valid && !io.fromDq(i).ready,
       p"pc 0x${Hexadecimal(io.fromDq(i).bits.cf.pc)} waits at Fp dispatch queue with index $i\n")
   }
+  XSError(PopCount(io.fromDq.map(_.fire())) =/= PopCount(io.enqIQCtrl.map(_.fire())), "deq =/= enq\n")
 
   /**
     * Part 5: the second stage of dispatch 2 (send data to reservation station)

src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala

@@ -21,48 +21,28 @@ class Dispatch2Int extends XSModule {
   /**
     * Part 1: generate indexes for reservation stations
     */
+  val jmpCanAccept = VecInit(io.fromDq.map(deq => deq.valid && jumpExeUnitCfg.canAccept(deq.bits.ctrl.fuType)))
+  val aluCanAccept = VecInit(io.fromDq.map(deq => deq.valid && aluExeUnitCfg.canAccept(deq.bits.ctrl.fuType)))
+  val mduCanAccept = VecInit(io.fromDq.map(deq => deq.valid && mulDivExeUnitCfg.canAccept(deq.bits.ctrl.fuType)))
   assert(exuParameters.JmpCnt == 1)
   val jmpIndexGen = Module(new IndexMapping(dpParams.IntDqDeqWidth, exuParameters.JmpCnt, false))
   val aluIndexGen = Module(new IndexMapping(dpParams.IntDqDeqWidth, exuParameters.AluCnt, true))
   val mduIndexGen = Module(new IndexMapping(dpParams.IntDqDeqWidth, exuParameters.MduCnt, true))
   val aluPriority = PriorityGen((0 until exuParameters.AluCnt).map(i => io.numExist(i+exuParameters.JmpCnt)))
   val mduPriority = PriorityGen((0 until exuParameters.MduCnt).map(i => io.numExist(i+exuParameters.JmpCnt+exuParameters.AluCnt)))
-  for (i <- 0 until dpParams.IntDqDeqWidth) {
-    jmpIndexGen.io.validBits(i) := io.fromDq(i).valid && jumpExeUnitCfg.canAccept(io.fromDq(i).bits.ctrl.fuType)
-    aluIndexGen.io.validBits(i) := io.fromDq(i).valid && aluExeUnitCfg.canAccept(io.fromDq(i).bits.ctrl.fuType)
-    mduIndexGen.io.validBits(i) := io.fromDq(i).valid && mulDivExeUnitCfg.canAccept(io.fromDq(i).bits.ctrl.fuType)
-    // XSDebug(io.fromDq(i).valid,
-    //   p"int dp queue $i: ${Hexadecimal(io.fromDq(i).bits.cf.pc)} type ${Binary(io.fromDq(i).bits.ctrl.fuType)}\n")
-  }
+  jmpIndexGen.io.validBits := jmpCanAccept
+  aluIndexGen.io.validBits := aluCanAccept
+  mduIndexGen.io.validBits := mduCanAccept
   jmpIndexGen.io.priority := DontCare
-  for (i <- 0 until exuParameters.AluCnt) {
-    aluIndexGen.io.priority(i) := aluPriority(i)
-  }
-  for (i <- 0 until exuParameters.MduCnt) {
-    mduIndexGen.io.priority(i) := mduPriority(i)
-  }
+  aluIndexGen.io.priority := aluPriority
+  mduIndexGen.io.priority := mduPriority
+
   val allIndexGen = Seq(jmpIndexGen, aluIndexGen, mduIndexGen)
   val validVec = allIndexGen.map(_.io.mapping.map(_.valid)).reduceLeft(_ ++ _)
   val indexVec = allIndexGen.map(_.io.mapping.map(_.bits)).reduceLeft(_ ++ _)
-  val rsValidVec = (0 until dpParams.IntDqDeqWidth).map(i => Cat(allIndexGen.map(_.io.reverseMapping(i).valid)).orR())
-  val rsIndexVec = (0 until dpParams.IntDqDeqWidth).map({i =>
-    val indexOffset = Seq(0, exuParameters.JmpCnt, exuParameters.JmpCnt + exuParameters.AluCnt)
-    allIndexGen.zipWithIndex.map{
-      case (index, j) => Mux(index.io.reverseMapping(i).valid,
-        ZeroExt(index.io.reverseMapping(i).bits, log2Ceil(exuParameters.IntExuCnt)) + indexOffset(j).U,
-        0.U)
-    }.reduce(_ | _)
-  })
-
   for (i <- validVec.indices) {
     // XSDebug(p"mapping $i: valid ${validVec(i)} index ${indexVec(i)}\n")
   }
-  for (i <- rsValidVec.indices) {
-    // XSDebug(p"jmp reverse $i: valid ${jmpIndexGen.io.reverseMapping(i).valid} index ${jmpIndexGen.io.reverseMapping(i).bits}\n")
-    // XSDebug(p"alu reverse $i: valid ${aluIndexGen.io.reverseMapping(i).valid} index ${aluIndexGen.io.reverseMapping(i).bits}\n")
-    // XSDebug(p"mdu reverse $i: valid ${mduIndexGen.io.reverseMapping(i).valid} index ${mduIndexGen.io.reverseMapping(i).bits}\n")
-    // XSDebug(p"reverseMapping $i: valid ${rsValidVec(i)} index ${rsIndexVec(i)}\n")
-  }
 
   /**
     * Part 2: assign regfile read ports
@@ -86,9 +66,20 @@ class Dispatch2Int extends XSModule {
   /**
     * Part 3: dispatch to reservation stations
     */
+  val jmpReady = io.enqIQCtrl(0).ready
+  val aluReady = Cat(io.enqIQCtrl.take(exuParameters.JmpCnt + exuParameters.AluCnt).drop(exuParameters.JmpCnt).map(_.ready)).andR
+  val mduReady = Cat(io.enqIQCtrl.drop(exuParameters.JmpCnt + exuParameters.AluCnt).map(_.ready)).andR
   for (i <- 0 until exuParameters.IntExuCnt) {
     val enq = io.enqIQCtrl(i)
-    enq.valid := validVec(i)
+    if (i < exuParameters.JmpCnt) {
+      enq.valid := jmpIndexGen.io.mapping(i).valid// && jmpReady
+    }
+    else if (i < exuParameters.JmpCnt + exuParameters.AluCnt) {
+      enq.valid := aluIndexGen.io.mapping(i - exuParameters.JmpCnt).valid && aluReady
+    }
+    else {
+      enq.valid := mduIndexGen.io.mapping(i - (exuParameters.JmpCnt + exuParameters.AluCnt)).valid && mduReady
+    }
     enq.bits := io.fromDq(indexVec(i)).bits
     enq.bits.src1State := io.regRdy(readPortIndex(i))
     enq.bits.src2State := io.regRdy(readPortIndex(i) + 1.U)
@@ -101,14 +92,19 @@ class Dispatch2Int extends XSModule {
   /**
     * Part 4: response to dispatch queue
     */
+  val mdu2CanOut = !(mduCanAccept(0) && mduCanAccept(1))
+  val mdu3CanOut = !(mduCanAccept(0) && mduCanAccept(1) || mduCanAccept(0) && mduCanAccept(2) || mduCanAccept(1) && mduCanAccept(2))
   for (i <- 0 until dpParams.IntDqDeqWidth) {
-    io.fromDq(i).ready := rsValidVec(i) && io.enqIQCtrl(rsIndexVec(i)).ready
+    io.fromDq(i).ready := jmpCanAccept(i) && (if (i == 0) true.B else !Cat(jmpCanAccept.take(i)).orR) && jmpReady ||
+                          aluCanAccept(i) && aluReady ||
+                          mduCanAccept(i) && (if (i <= 1) true.B else if (i == 2) mdu2CanOut else mdu3CanOut) && mduReady
 
     XSInfo(io.fromDq(i).fire(),
       p"pc 0x${Hexadecimal(io.fromDq(i).bits.cf.pc)} leaves Int dispatch queue $i with nroq ${io.fromDq(i).bits.roqIdx}\n")
     XSDebug(io.fromDq(i).valid && !io.fromDq(i).ready,
       p"pc 0x${Hexadecimal(io.fromDq(i).bits.cf.pc)} waits at Int dispatch queue with index $i\n")
   }
+  XSError(PopCount(io.fromDq.map(_.fire())) =/= PopCount(io.enqIQCtrl.map(_.fire())), "deq =/= enq\n")
 
   /**
     * Part 5: the second stage of dispatch 2 (send data to reservation station)

src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala

@@ -25,43 +25,23 @@ class Dispatch2Ls extends XSModule {
     * Part 1: generate indexes for reservation stations
     */
   val loadIndexGen = Module(new IndexMapping(dpParams.LsDqDeqWidth, exuParameters.LduCnt, true))
-  val storeIndexGen = Module(new IndexMapping(dpParams.LsDqDeqWidth, exuParameters.StuCnt, true))
+  val loadCanAccept = VecInit(io.fromDq.map(deq => deq.valid && ldExeUnitCfg.canAccept(deq.bits.ctrl.fuType)))
   val loadPriority = PriorityGen((0 until exuParameters.LduCnt).map(i => io.numExist(i)))
+  loadIndexGen.io.validBits := loadCanAccept
+  loadIndexGen.io.priority := loadPriority
+
+  val storeIndexGen = Module(new IndexMapping(dpParams.LsDqDeqWidth, exuParameters.StuCnt, true))
+  val storeCanAccept = VecInit(io.fromDq.map(deq => deq.valid && stExeUnitCfg.canAccept(deq.bits.ctrl.fuType)))
   val storePriority = PriorityGen((0 until exuParameters.StuCnt).map(i => io.numExist(i+exuParameters.LduCnt)))
-  for (i <- 0 until dpParams.LsDqDeqWidth) {
-    loadIndexGen.io.validBits(i) := io.fromDq(i).valid && ldExeUnitCfg.canAccept(io.fromDq(i).bits.ctrl.fuType)
-    storeIndexGen.io.validBits(i) := io.fromDq(i).valid && stExeUnitCfg.canAccept(io.fromDq(i).bits.ctrl.fuType)
+  storeIndexGen.io.validBits := storeCanAccept
+  storeIndexGen.io.priority := storePriority
 
-    // XSDebug(io.fromDq(i).valid,
-    //   p"ls dp queue $i: ${Hexadecimal(io.fromDq(i).bits.cf.pc)} type ${Binary(io.fromDq(i).bits.ctrl.fuType)}\n")
-  }
-  for (i <- 0 until exuParameters.LduCnt) {
-    loadIndexGen.io.priority(i) := loadPriority(i)
-  }
-  for (i <- 0 until exuParameters.StuCnt) {
-    storeIndexGen.io.priority(i) := storePriority(i)
-  }
   val allIndexGen = Seq(loadIndexGen, storeIndexGen)
   val validVec = allIndexGen.map(_.io.mapping.map(_.valid)).reduceLeft(_ ++ _)
   val indexVec = allIndexGen.map(_.io.mapping.map(_.bits)).reduceLeft(_ ++ _)
-  val rsValidVec = (0 until dpParams.LsDqDeqWidth).map(i => Cat(allIndexGen.map(_.io.reverseMapping(i).valid)).orR())
-  val rsIndexVec = (0 until dpParams.LsDqDeqWidth).map({i =>
-    val indexOffset = Seq(0, exuParameters.LduCnt)
-    allIndexGen.zipWithIndex.map{
-      case (index, j) => Mux(index.io.reverseMapping(i).valid,
-        ZeroExt(index.io.reverseMapping(i).bits, log2Ceil(exuParameters.LsExuCnt)) + indexOffset(j).U,
-        0.U)
-    }.reduce(_ | _)
-  })
-
   for (i <- validVec.indices) {
     // XSDebug(p"mapping $i: valid ${validVec(i)} index ${indexVec(i)}\n")
   }
-  for (i <- rsValidVec.indices) {
-    // XSDebug(p"load reverse $i: valid ${loadIndexGen.io.reverseMapping(i).valid} index ${loadIndexGen.io.reverseMapping(i).bits}\n")
-    // XSDebug(p"store reverse $i: valid ${storeIndexGen.io.reverseMapping(i).valid} index ${storeIndexGen.io.reverseMapping(i).bits}\n")
-    // XSDebug(p"reverseMapping $i: valid ${rsValidVec(i)} index ${rsIndexVec(i)}\n")
-  }
 
   /**
     * Part 2: assign regfile read ports (actually only reg states from rename)
@@ -85,9 +65,16 @@ class Dispatch2Ls extends XSModule {
   /**
     * Part 3: dispatch to reservation stations
     */
+  val loadReady = Cat(io.enqIQCtrl.take(exuParameters.LduCnt).map(_.ready)).andR
+  val storeReady = Cat(io.enqIQCtrl.drop(exuParameters.LduCnt).map(_.ready)).andR
   for (i <- 0 until exuParameters.LsExuCnt) {
     val enq = io.enqIQCtrl(i)
-    enq.valid := validVec(i)
+    if (i < exuParameters.LduCnt) {
+      enq.valid := loadIndexGen.io.mapping(i).valid && loadReady
+    }
+    else {
+      enq.valid := storeIndexGen.io.mapping(i - exuParameters.LduCnt).valid && storeReady
+    }
     enq.bits := io.fromDq(indexVec(i)).bits
     enq.bits.src1State := io.intRegRdy(readPort(i))
     if (i < exuParameters.LduCnt) {
@@ -106,14 +93,20 @@ class Dispatch2Ls extends XSModule {
   /**
     * Part 4: response to dispatch queue
     */
+  val load2CanOut = !(loadCanAccept(0) && loadCanAccept(1))
+  val load3CanOut = !(loadCanAccept(0) && loadCanAccept(1) || loadCanAccept(0) && loadCanAccept(2) || loadCanAccept(1) && loadCanAccept(2))
+  val store2CanOut = !(storeCanAccept(0) && storeCanAccept(1))
+  val store3CanOut = !(storeCanAccept(0) && storeCanAccept(1) || storeCanAccept(0) && storeCanAccept(2) || storeCanAccept(1) && storeCanAccept(2))
   for (i <- 0 until dpParams.LsDqDeqWidth) {
-    io.fromDq(i).ready := rsValidVec(i) && io.enqIQCtrl(rsIndexVec(i)).ready
+    io.fromDq(i).ready := loadCanAccept(i) && (if (i <= 1) true.B else if (i == 2) load2CanOut else load3CanOut) && loadReady ||
+                          storeCanAccept(i) && (if (i <= 1) true.B else if (i == 2) store2CanOut else store3CanOut) && storeReady
 
     XSInfo(io.fromDq(i).fire(),
       p"pc 0x${Hexadecimal(io.fromDq(i).bits.cf.pc)} leaves Ls dispatch queue $i with nroq ${io.fromDq(i).bits.roqIdx}\n")
     XSDebug(io.fromDq(i).valid && !io.fromDq(i).ready,
       p"pc 0x${Hexadecimal(io.fromDq(i).bits.cf.pc)} waits at Ls dispatch queue with index $i\n")
   }
+  XSError(PopCount(io.fromDq.map(_.fire())) =/= PopCount(io.enqIQCtrl.map(_.fire())), "deq =/= enq\n")
 
   /**
     * Part 5: the second stage of dispatch 2 (send data to reservation station)