ras: fix a bug where ras pushes wrong pc into stack on last half rvi-call

now we have reasonable ras performance on rvc coremark

src/main/scala/xiangshan/frontend/BPU.scala

@@ -330,6 +330,7 @@ class BPUStage3 extends BPUStage {
     ras.io.callIdx.valid := calls.orR && (callIdx === jmpIdx) && io.predecode.valid
     ras.io.callIdx.bits := callIdx
     ras.io.isRVC := (calls & RVCs).orR   //TODO: this is ugly
+    ras.io.isLastHalfRVI := !io.predecode.bits.isFetchpcEqualFirstpc
     ras.io.recover := io.recover
 
     for(i <- 0 until PredictWidth){

src/main/scala/xiangshan/frontend/RAS.scala

@@ -25,6 +25,7 @@ class RAS extends BasePredictor
         val is_ret = Input(Bool())
         val callIdx = Flipped(ValidIO(UInt(log2Ceil(PredictWidth).W)))
         val isRVC = Input(Bool())
+        val isLastHalfRVI = Input(Bool())
         val recover =  Flipped(ValidIO(new BranchUpdateInfo))
         val out = ValidIO(new RASResp)
         val branchInfo = Output(new RASBranchInfo)
@@ -69,7 +70,7 @@ class RAS extends BasePredictor
     // speculative update RAS
     val spec_push = !spec_is_full && io.callIdx.valid && io.pc.valid
     val spec_pop = !spec_is_empty && io.is_ret && io.pc.valid
-    val spec_new_addr = io.pc.bits + (io.callIdx.bits << 1.U) + Mux(io.isRVC,2.U,4.U)
+    val spec_new_addr = io.pc.bits + (io.callIdx.bits << 1.U) + Mux(io.isRVC,2.U,Mux(io.isLastHalfRVI, 2.U, 4.U))
     val spec_ras_write = WireInit(0.U.asTypeOf(rasEntry()))
     val sepc_alloc_new = spec_new_addr =/= spec_ras_top_addr
     when (spec_push) {