Merge branch 'dev-soc' of github.com:RISCVERS/XiangShan into dev-lsu

Makefile

@@ -134,4 +134,9 @@ cache:
 clean:
 	rm -rf $(BUILD_DIR)
 
-.PHONY: verilog emu clean help $(REF_SO)
+init:
+	git submodule update --init
+	# do not use a recursive init to pull some not used submodules
+	cd ./rocket-chip/ && git submodule update --init api-config-chipsalliance hardfloat
+
+.PHONY: verilog emu clean help init $(REF_SO)

README.md

@@ -6,6 +6,7 @@ Currently it only supports riscv32.
 ## Compile chisel code
 
 * Install `mill`. Refer to [the Manual section in this guide][mill].
+* Run `make init` to init git submodules
 * Run `make` to generate verilog code. The output file is `build/TopMain.v`.
 
 [mill]: http://lihaoyi.com/mill#manual