Update parameters as demanded.

src/main/scala/system/SoC.scala

@@ -80,6 +80,7 @@ class ILABundle extends Bundle {}
 
 
 abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
+  val PAddrBits = p(SoCParamsKey).PAddrBits
   val bankedNode = BankBinder(L3NBanks, L3BlockSize)
   val peripheralXbar = TLXbar()
   val l3_xbar = TLXbar()
@@ -130,8 +131,8 @@ trait HaveSlaveAXI4Port {
 trait HaveAXI4MemPort {
   this: BaseSoC =>
   val device = new MemoryDevice
-  // 36-bit physical address
-  val memRange = AddressSet(0x00000000L, 0xfffffffffL).subtract(AddressSet(0x0L, 0x7fffffffL))
+  val addrMask = (1L << PAddrBits) - 1L
+  val memRange = AddressSet(0x00000000L, addrMask).subtract(AddressSet(0x0L, 0x7fffffffL))
   val memAXI4SlaveNode = AXI4SlaveNode(Seq(
     AXI4SlavePortParameters(
       slaves = Seq(

src/main/scala/top/Configs.scala

@@ -36,7 +36,7 @@ import huancun._
 class BaseConfig(n: Int) extends Config((site, here, up) => {
   case XLen => 64
   case DebugOptionsKey => DebugOptions()
-  case SoCParamsKey => SoCParameters()
+  case SoCParamsKey => SoCParameters(PAddrBits = 53, extIntrs = 256)
   case PMParameKey => PMParameters()
   case XSTileKey => Seq.tabulate(n){
     i => XSCoreParameters(HartId = i, hasMbist = true, hasShareBus = true)
@@ -201,7 +201,7 @@ class MinimalSimConfig(n: Int = 1) extends Config(
   })
 )
 
-class WithNKBL1D(n: Int, ways: Int = 4) extends Config((site, here, up) => {
+class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => {
   case XSTileKey =>
     val sets = n * 1024 / ways / 64
     up(XSTileKey).map(_.copy(
@@ -314,6 +314,6 @@ class MediumConfig(n: Int = 1) extends Config(
 class DefaultConfig(n: Int = 1) extends Config(
   new WithNKBL3(6 * 1024, inclusive = false, banks = 4, ways = 6)
     ++ new WithNKBL2(2 * 512, inclusive = false, banks = 4, alwaysReleaseData = true)
-    ++ new WithNKBL1D(64)
+    ++ new WithNKBL1D(128)
     ++ new BaseConfig(n)
 )