lsroq: send oldest miss dcache request first

src/main/scala/xiangshan/mem/Lsroq.scala

@@ -174,7 +174,7 @@ class Lsroq extends XSModule {
   val missRefillSelVec = VecInit(
     (0 until LsroqSize).map(i => allocated(i) && miss(i))
   )
-  val missRefillSel = PriorityEncoder(missRefillSelVec.asUInt)
+  val missRefillSel = getFirstOne(missRefillSelVec, ringBufferTail)
   io.dcache.req.valid := missRefillSelVec.asUInt.orR
   io.dcache.req.bits.cmd := MemoryOpConstants.M_XRD
   io.dcache.req.bits.addr := data(missRefillSel).paddr