[WIP] update frontend interface

src/main/scala/xiangshan/Bundle.scala

@@ -196,10 +196,13 @@ class FtqEntry extends XSBundle {
     val rasTop = new RASEntry()
     val metas = Vec(PredictWidth, new BpuMeta)
 
-    val brMask = UInt(PredictWidth.W)
-    val jalMask = UInt(PredictWidth.W)
+    val brMask = Vec(PredictWidth, Bool())
+    val jalMask = Vec(PredictWidth, Bool())
 
-    val mispred = UInt(PredictWidth.W)
+    // backend update
+    val mispred = Vec(PredictWidth, Bool())
+    val taken = Vec(PredictWidth, Bool())
+    val jalr_target = UInt(VAddrBits.W)
 }
 
 
@@ -285,8 +288,7 @@ class Redirect extends XSBundle {
   val roqIdx = new RoqPtr
   val level = RedirectLevel()
   val interrupt = Bool()
-  val pc = UInt(VAddrBits.W)
-  val target = UInt(VAddrBits.W)
+  val cfiUpdate = new CfiUpdateInfo
 
   def isUnconditional() = RedirectLevel.isUnconditional(level)
   def flushItself() = RedirectLevel.flushItself(level)
@@ -377,8 +379,8 @@ class FrontendToBackendIO extends XSBundle {
   val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow))
   val fetchInfo = DecoupledIO(new FtqEntry)
   // from backend
-  val redirect_cfiUpdate = Flipped(ValidIO(new CfiUpdateInfo))
-  val commit_cfiUpdate = Flipped(Vec(CommitWidth, ValidIO(new CfiUpdateInfo)))
+  val redirect_cfiUpdate = Flipped(ValidIO(new Redirect))
+  val commit_cfiUpdate = Flipped(ValidIO(new FtqEntry))
 }
 
 class TlbCsrBundle extends XSBundle {

src/main/scala/xiangshan/backend/CtrlBlock.scala

@@ -166,7 +166,7 @@ class CtrlBlock extends XSModule with HasCircularQueuePtrHelper {
   fpBusyTable.io.pregRdy <> dispatch.io.fpPregRdy
 
   roq.io.redirect <> backendRedirect
-  roq.io.exeWbResults.take(roqWbSize-1).zip(
+  roq.io.exeWbResults.zip(
     io.fromIntBlock.wbRegs ++ io.fromFpBlock.wbRegs ++ io.fromLsBlock.stOut
   ).foreach{
     case(x, y) =>

src/main/scala/xiangshan/backend/ftq/Ftq.scala

@@ -37,12 +37,12 @@ class Ftq extends XSModule with HasCircularQueuePtrHelper with NeedImpl {
     val enqPtr = Output(new FtqPtr)
     // roq commit, read out fectch packet and deq
     val roq_commits = Vec(CommitWidth, ValidIO(new RoqCommitInfo))
-    val commit_cfiUpdate = Vec(CommitWidth, ValidIO(new CfiUpdateInfo))
+    val commit_ftqEntry = ValidIO(new FtqEntry)
     // redirect, reset enq ptr
     val redirect = Input(ValidIO(new Redirect))
     // exu write back, update info
     val exuWriteback = Vec(exuParameters.JmpCnt + exuParameters.AluCnt, Flipped(ValidIO(new ExuOutput)))
-    // pc read reqs (1 for load replay / exceptions, 1 for jump/auipc, 1 for misprediction)
+    // pc read reqs (0: jump/auipc 1: redirect 2: load replay / exceptions)
     val ftqRead = Vec(3, Flipped(new FtqRead))
   })
 
@@ -58,4 +58,7 @@ class Ftq extends XSModule with HasCircularQueuePtrHelper with NeedImpl {
 
 
 
+
+
+
 }