StoreMissQueue: added some debug logs.

src/main/scala/xiangshan/cache/storeMissQueue.scala

@@ -54,7 +54,7 @@ class StoreMissEntry extends DCacheModule
 
 
   when (state =/= s_invalid) {
-    XSDebug("entry: %d state: %d\n", io.id, state)
+    XSDebug("entry: %d state: %d idx: %x tag: %x\n", io.id, state, io.idx.bits, io.tag.bits)
   }
 
   // --------------------------------------------
@@ -164,6 +164,7 @@ class StoreMissQueue extends DCacheModule
   val tag_match   = Mux1H(idx_matches, tag_matches)
   val idx_match   = idx_matches.reduce(_||_)
 
+  XSDebug("idx_match: %b tag_match: %b\n", idx_match, tag_match)
 
   val req             = io.lsu.req
   val entry_alloc_idx = Wire(UInt())