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体验新版 GitCode,发现更多精彩内容 >>
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bfa46a82
编写于
12月 17, 2020
作者:
Y
Yinan Xu
提交者:
GitHub
12月 17, 2020
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差异文件
Merge pull request #327 from RISCVERS/debian-gogogo
roq, icache, storeUnit, emu, dtlb: bug fixes
上级
c3ece97f
f698fe9c
变更
6
隐藏空白更改
内联
并排
Showing
6 changed file
with
45 addition
and
21 deletion
+45
-21
src/main/scala/xiangshan/backend/roq/Roq.scala
src/main/scala/xiangshan/backend/roq/Roq.scala
+1
-0
src/main/scala/xiangshan/cache/dtlb.scala
src/main/scala/xiangshan/cache/dtlb.scala
+28
-17
src/main/scala/xiangshan/cache/icache.scala
src/main/scala/xiangshan/cache/icache.scala
+1
-1
src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
+1
-1
src/test/csrc/compress.cpp
src/test/csrc/compress.cpp
+9
-2
src/test/csrc/emu.cpp
src/test/csrc/emu.cpp
+5
-0
未找到文件。
src/main/scala/xiangshan/backend/roq/Roq.scala
浏览文件 @
bfa46a82
...
...
@@ -365,6 +365,7 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
// when exception occurs, cancels all
when
(
io
.
redirect
.
valid
)
{
// TODO: need check for flushPipe
state
:=
s_idle
enqPtrExt
:=
0.
U
.
asTypeOf
(
new
RoqPtr
)
deqPtrExt
:=
0.
U
.
asTypeOf
(
new
RoqPtr
)
}
...
...
src/main/scala/xiangshan/cache/dtlb.scala
浏览文件 @
bfa46a82
...
...
@@ -273,8 +273,32 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
val
entry
=
Reg
(
Vec
(
TlbEntrySize
,
new
TlbEntry
))
val
g
=
VecInit
(
entry
.
map
(
_
.
perm
.
g
)).
asUInt
// TODO: need check if reverse is needed
/**
* PTW refill
*/
val
refill
=
ptw
.
resp
.
fire
()
val
randIdx
=
LFSR64
()(
log2Up
(
TlbEntrySize
)-
1
,
0
)
val
priorIdx
=
PriorityEncoder
(~(
v
|
pf
))
val
tlbfull
=
ParallelAND
((
v
|
pf
).
asBools
)
val
refillIdx
=
Mux
(
tlbfull
,
randIdx
,
priorIdx
)
val
refillIdxOH
=
UIntToOH
(
refillIdx
)
when
(
refill
)
{
v
:=
Mux
(
ptw
.
resp
.
bits
.
pf
,
v
&
~
refillIdxOH
,
v
|
refillIdxOH
)
entry
(
refillIdx
)
:=
ptw
.
resp
.
bits
.
entry
XSDebug
(
p
"Refill: idx:${refillIdx} entry:${ptw.resp.bits.entry}\n"
)
}
/**
* L1 TLB read
*/
val
tlb_read_mask
=
Mux
(
refill
,
refillIdxOH
,
0.
U
(
TlbEntrySize
.
W
))
def
TLBRead
(
i
:
Int
)
=
{
val
entryHitVec
=
VecInit
(
entry
.
map
(
_
.
hit
(
reqAddr
(
i
).
vpn
/*, satp.asid*/
)))
val
entryHitVec
=
(
if
(
isDtlb
)
VecInit
((
tlb_read_mask
.
asBools
zip
entry
).
map
{
case
(
r
,
e
)
=>
!
r
&&
e
.
hit
(
reqAddr
(
i
).
vpn
/*, satp.asid*/
)})
else
VecInit
(
entry
.
map
(
_
.
hit
(
reqAddr
(
i
).
vpn
/*, satp.asid*/
)))
)
val
reqAddrReg
=
if
(
isDtlb
)
RegNext
(
reqAddr
(
i
))
else
reqAddr
(
i
)
val
cmdReg
=
if
(
isDtlb
)
RegNext
(
cmd
(
i
))
else
cmd
(
i
)
...
...
@@ -364,25 +388,12 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
val
pfHitReset
=
ParallelOR
(
widthMap
{
i
=>
Mux
(
resp
(
i
).
fire
(),
VecInit
(
pfHitVecVec
(
i
)).
asUInt
,
0.
U
)
})
val
pfHitRefill
=
ParallelOR
(
pfHitReset
.
asBools
)
// refill
val
refill
=
ptw
.
resp
.
fire
()
val
randIdx
=
LFSR64
()(
log2Up
(
TlbEntrySize
)-
1
,
0
)
val
priorIdx
=
PriorityEncoder
(~(
v
|
pf
))
val
tlbfull
=
ParallelAND
((
v
|
pf
).
asBools
)
val
refillIdx
=
Mux
(
tlbfull
,
randIdx
,
priorIdx
)
val
re2OH
=
UIntToOH
(
refillIdx
)
when
(
refill
)
{
v
:=
Mux
(
ptw
.
resp
.
bits
.
pf
,
v
&
~
re2OH
,
v
|
re2OH
)
entry
(
refillIdx
)
:=
ptw
.
resp
.
bits
.
entry
XSDebug
(
p
"Refill: idx:${refillIdx} entry:${ptw.resp.bits.entry}\n"
)
}
// pf update
when
(
refill
)
{
when
(
pfHitRefill
)
{
pf
:=
Mux
(
ptw
.
resp
.
bits
.
pf
,
pf
|
re
2OH
,
pf
&
~
re2
OH
)
&
~
pfHitReset
pf
:=
Mux
(
ptw
.
resp
.
bits
.
pf
,
pf
|
re
fillIdxOH
,
pf
&
~
refillIdx
OH
)
&
~
pfHitReset
}
.
otherwise
{
pf
:=
Mux
(
ptw
.
resp
.
bits
.
pf
,
pf
|
re
2OH
,
pf
&
~
re2
OH
)
pf
:=
Mux
(
ptw
.
resp
.
bits
.
pf
,
pf
|
re
fillIdxOH
,
pf
&
~
refillIdx
OH
)
}
}
.
otherwise
{
when
(
pfHitRefill
)
{
...
...
@@ -390,7 +401,7 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
}
}
when
(
PopCount
(
pf
)
>
10.
U
)
{
// when too much pf, just clear
pf
:=
Mux
(
refill
&&
ptw
.
resp
.
bits
.
pf
,
re
2
OH
,
0.
U
)
pf
:=
Mux
(
refill
&&
ptw
.
resp
.
bits
.
pf
,
re
fillIdx
OH
,
0.
U
)
}
// sfence (flush)
...
...
src/main/scala/xiangshan/cache/icache.scala
浏览文件 @
bfa46a82
...
...
@@ -311,7 +311,7 @@ class ICache extends ICacheModule
//physical address < 0x80000000
//TODO: May have bugs
s2_access_fault
:=
(
s2_tlb_resp
.
paddr
(
31
,
0
)
<
accessBorder
.
U
(
31
,
0
)
)
&&
s2_valid
s2_access_fault
:=
(
s2_tlb_resp
.
paddr
<
accessBorder
.
U
)
&&
s2_valid
// SRAM(Meta and Data) read reseponse
val
metas
=
metaArray
.
io
.
readResp
...
...
src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
浏览文件 @
bfa46a82
...
...
@@ -76,7 +76,7 @@ class StoreUnit_S1 extends XSModule {
// get paddr from dtlb, check if rollback is needed
// writeback store inst to lsq
io
.
lsq
.
valid
:=
io
.
in
.
valid
// TODO: && ! FP
io
.
lsq
.
valid
:=
io
.
in
.
valid
&&
!
s1_tlb_miss
// TODO: && ! FP
io
.
lsq
.
bits
:=
io
.
in
.
bits
io
.
lsq
.
bits
.
paddr
:=
s1_paddr
io
.
lsq
.
bits
.
miss
:=
false
.
B
...
...
src/test/csrc/compress.cpp
浏览文件 @
bfa46a82
...
...
@@ -74,7 +74,9 @@ long readFromGz(void* ptr, const char *file_name, long buf_size, uint8_t load_ty
while
(
curr_size
<
buf_size
)
{
uint32_t
bytes_read
=
gzread
(
compressed_mem
,
temp_page
,
chunk_size
);
if
(
bytes_read
==
0
)
{
break
;
}
if
(
bytes_read
==
0
)
{
break
;
}
assert
(
load_type
!=
LOAD_RAM
||
bytes_read
%
sizeof
(
long
)
==
0
);
for
(
uint32_t
x
=
0
;
x
<
bytes_read
/
sizeof
(
long
)
+
1
;
x
++
)
{
if
(
*
(
temp_page
+
x
)
!=
0
)
{
...
...
@@ -84,6 +86,11 @@ long readFromGz(void* ptr, const char *file_name, long buf_size, uint8_t load_ty
}
curr_size
+=
bytes_read
;
}
if
(
gzread
(
compressed_mem
,
temp_page
,
chunk_size
)
>
0
)
{
printf
(
"File size is larger than RAMSIZE!
\n
"
);
assert
(
0
);
}
printf
(
"Read %lu bytes from gz stream in total
\n
"
,
curr_size
);
delete
[]
temp_page
;
...
...
@@ -93,4 +100,4 @@ long readFromGz(void* ptr, const char *file_name, long buf_size, uint8_t load_ty
return
-
1
;
}
return
curr_size
;
}
\ No newline at end of file
}
src/test/csrc/emu.cpp
浏览文件 @
bfa46a82
...
...
@@ -194,7 +194,11 @@ inline void Emulator::single_cycle() {
#ifdef WITH_DRAMSIM3
axi_channel
axi
;
axi_copy_from_dut_ptr
(
dut_ptr
,
axi
);
axi
.
aw
.
addr
-=
0x80000000UL
;
axi
.
ar
.
addr
-=
0x80000000UL
;
dramsim3_helper
(
axi
);
axi
.
aw
.
addr
+=
0x80000000UL
;
axi
.
ar
.
addr
+=
0x80000000UL
;
axi_set_dut_ptr
(
dut_ptr
,
axi
);
#endif
...
...
@@ -322,6 +326,7 @@ uint64_t Emulator::execute(uint64_t max_cycle, uint64_t max_instr) {
}
if
(
Verilated
::
gotFinish
())
{
difftest_display
(
dut_ptr
->
io_difftest_priviledgeMode
);
eprintf
(
"The simulation stopped. There might be some assertion failed.
\n
"
);
trapCode
=
STATE_ABORT
;
}
...
...
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