提交 ba4100ca 编写于 作者: Y Yinan Xu

perf: add debug info for timer

上级 49cdb253
......@@ -159,12 +159,22 @@ trait HasRoqIdx { this: HasXSParameter =>
}
}
class PerfDebugInfo extends XSBundle {
// val fetchTime = UInt(64.W)
val renameTime = UInt(64.W)
val inRoqTime = UInt(64.W)
val issueTime = UInt(64.W)
val writebackTime = UInt(64.W)
val commitTime = UInt(64.W)
}
// CfCtrl -> MicroOp at Rename Stage
class MicroOp extends CfCtrl with HasRoqIdx {
val psrc1, psrc2, psrc3, pdest, old_pdest = UInt(PhyRegIdxWidth.W)
val src1State, src2State, src3State = SrcState()
val lsroqIdx = UInt(LsroqIdxWidth.W)
val diffTestDebugLrScValid = Bool()
val debugInfo = PerfDebugInfo()
}
class Redirect extends XSBundle with HasRoqIdx {
......
......@@ -76,6 +76,7 @@ class Rename extends XSModule {
// debug assert
val outRdy = Cat(io.out.map(_.ready))
assert(outRdy===0.U || outRdy.andR())
val timer = GTimer()
for(i <- 0 until RenameWidth) {
uops(i).cf := io.in(i).bits.cf
uops(i).ctrl := io.in(i).bits.ctrl
......@@ -119,6 +120,7 @@ class Rename extends XSModule {
io.out(i).valid := io.in(i).fire()
io.out(i).bits := uops(i)
io.out(i).bits.debugInfo.renameTime = timer
// write rename table
def writeRat(fp: Boolean) = {
......
......@@ -56,6 +56,7 @@ class Roq extends XSModule {
val hasNoSpec = RegInit(false.B)
when(isEmpty){ hasNoSpec:= false.B }
val validDispatch = io.dp1Req.map(_.valid)
val timer = GTimer()
XSDebug("(ready, valid): ")
for (i <- 0 until RenameWidth) {
val offset = PopCount(validDispatch.take(i))
......@@ -64,6 +65,7 @@ class Roq extends XSModule {
when(io.dp1Req(i).fire()){
microOp(roqIdx) := io.dp1Req(i).bits
microOp(roqIdx).debugInfo.inRoqTime := timer
valid(roqIdx) := true.B
flag(roqIdx) := roqIdxExt.head(1).asBool()
writebacked(roqIdx) := false.B
......@@ -94,6 +96,7 @@ class Roq extends XSModule {
writebacked(wbIdx) := true.B
microOp(wbIdx).cf.exceptionVec := io.exeWbResults(i).bits.uop.cf.exceptionVec
microOp(wbIdx).lsroqIdx := io.exeWbResults(i).bits.uop.lsroqIdx
microOp(wbIdx).debugInfo.writebackTime := timer
microOp(wbIdx).ctrl.flushPipe := io.exeWbResults(i).bits.uop.ctrl.flushPipe
microOp(wbIdx).diffTestDebugLrScValid := io.exeWbResults(i).bits.uop.diffTestDebugLrScValid
exuData(wbIdx) := io.exeWbResults(i).bits.data
......
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