nothing, just change branch to mmu

src/main/scala/noop/TLB.scala

@@ -134,7 +134,7 @@ sealed trait HasTlbConst {
   val Ways = tlbConfig.ways
   val Sets = 1
 
-  val debug = false//true //&& tlbname == "dtlb"
+  val debug = true && tlbname == "itlb"
 
   def TlbMetaArrayReadBus() = new SRAMReadBus(new TLBMetaBundle, set = Sets, way = Ways)
   def TlbDataArrayReadBus() = new SRAMReadBus(new TLBDataBundle, set = Sets, way = Ways)
@@ -379,6 +379,14 @@ sealed class TlbStage3(implicit val tlbConfig: TLBConfig) extends TlbModule with
   io.metaWriteBus.req <> metaRefillWriteBus.req
 
   io.out.bits.addr := Cat(0.U(paResLen.W), Cat(Mux(hit, dataRead, memStoreAddr.asTypeOf(pteBundle).ppn), req.addr.asTypeOf(vaBundle2).off))
+  
+  when(io.out.bits.addr === "h800027ac".U || io.out.bits.addr === "h800029e2".U) {
+    printf("%d find csrw sepc: vaddr:%x \n", GTimer(), req.addr)
+  }
+  when(io.out.bits.addr === "h800028d8".U || io.out.bits.addr === "h800029b8".U || io.out.bits.addr === "h80002a2a".U) {
+    printf("%d find csrr sepc: vaddr:%x \n", GTimer(), req.addr)
+  }
+
   io.out.bits.size := req.size
   io.out.bits.cmd := req.cmd
   io.out.bits.wmask := req.wmask
@@ -520,7 +528,7 @@ class TLBIOTran(userBits: Int = 0, name: String = "default") extends NOOPModule
 
   Debug() {
     when(true.B) {
-      if(name == "dtran") { printf("-----------------------------------------------------------------------------------------------\n")}
+      if(/*name == "dtran"*/ true) { printf("-----------------------------------------------------------------------------------------------\n")}
       printf("%d:" + name + "InReq(%d, %d) InResp(%d, %d) ", GTimer(), io.in.req.valid, io.in.req.ready, io.in.resp.valid, io.in.resp.ready)
       printf("\n%d:" + name, GTimer())
       printf(p"InReqBits:${io.in.req.bits}, InRespBits:${io.in.resp.bits}")

src/main/scala/noop/fu/CSR.scala

@@ -479,7 +479,7 @@ class CSR(implicit val p: NOOPConfig) extends NOOPModule with HasCSRConst{
     when(raiseExceptionIntr){
       printf("[CSR] raiseExceptionIntr! int/exc: pc %x int (%d):%x exc: (%d):%x\n",io.cfIn.pc, intrNO, io.cfIn.intrVec.asUInt, exceptionNO, raiseExceptionVec.asUInt)
     }
-    //printf("[CSR] Red(%d, %x) raiseExcepIntr:%d valid:%d instrValid:%x \n", io.redirect.valid, io.redirect.target, raiseExceptionIntr, valid, io.instrValid)
+    //printf("[CSR] Red(%d, %x) raiseExcepIntr:%d isSret:%d retTarget:%x sepc:%x delegs:%d cfInpc:%x valid:%d instrValid:%x \n", io.redirect.valid, io.redirect.target, raiseExceptionIntr, isSret, retTarget, sepc, delegs, io.cfIn.pc, valid, io.instrValid)
   }
 
   // Branch control
@@ -563,6 +563,15 @@ class CSR(implicit val p: NOOPConfig) extends NOOPModule with HasCSRConst{
   io.in.ready := true.B
   io.out.valid := valid
 
+  Debug() {
+    printf("[CSR2] Red(%d, %x) raiseExcepIntr:%d isSret:%d retTarget:%x sepc:%x delegs:%d deleg:%x cfInpc:%x valid:%d instrValid:%x \n", io.redirect.valid, io.redirect.target, raiseExceptionIntr, isSret, retTarget, sepc, delegS, deleg, io.cfIn.pc, valid, io.instrValid)
+  }
+
+  when(raiseExceptionIntr && delegS ) {
+    printf("[CSR2] Red(%d, %x) raiseExcepIntr:%d isSret:%d retTarget:%x sepc:%x delegs:%d deleg:%x cfInpc:%x valid:%d instrValid:%x \n", io.redirect.valid, io.redirect.target, raiseExceptionIntr, isSret, retTarget, sepc, delegS, deleg, io.cfIn.pc, valid, io.instrValid)
+    printf("[CSR3] sepc is writen!!! pc:%x time:%d\n", io.cfIn.pc, GTimer())
+  }
+
   // perfcnt
 
   val perfCntList = Map(

src/main/scala/utils/Debug.scala

@@ -7,7 +7,7 @@ import noop.NOOPConfig
 
 object Debug {
   def apply(flag: Boolean = NOOPConfig().EnableDebug, cond: Bool = true.B)(body: => Unit): Any =
-    if (flag) { when (cond && GTimer() > 5541500.U && false.B) { body } }
+    if (flag) { when (cond && GTimer() > 5541100.U) { body } }
 }
 
 object ShowType {