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体验新版 GitCode,发现更多精彩内容 >>
提交
b5f5fbe6
编写于
7月 12, 2020
作者:
Z
ZhangZifei
浏览文件
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浏览文件
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电子邮件补丁
差异文件
BPU: add temp perf counter
上级
f20e1609
变更
4
显示空白变更内容
内联
并排
Showing
4 changed file
with
54 addition
and
2 deletion
+54
-2
src/main/scala/xiangshan/backend/brq/Brq.scala
src/main/scala/xiangshan/backend/brq/Brq.scala
+13
-1
src/main/scala/xiangshan/backend/roq/Roq.scala
src/main/scala/xiangshan/backend/roq/Roq.scala
+3
-0
src/main/scala/xiangshan/frontend/BPU.scala
src/main/scala/xiangshan/frontend/BPU.scala
+37
-0
src/main/scala/xiangshan/frontend/Ibuffer.scala
src/main/scala/xiangshan/frontend/Ibuffer.scala
+1
-1
未找到文件。
src/main/scala/xiangshan/backend/brq/Brq.scala
浏览文件 @
b5f5fbe6
...
...
@@ -4,7 +4,7 @@ import chisel3._
import
chisel3.util._
import
xiangshan._
import
xiangshan.utils._
import
chisel3.util.experimental.BoringUtils
class
BrqPtr
extends
XSBundle
{
...
...
@@ -221,4 +221,16 @@ class Brq extends XSModule {
XSInfo
(
debug_roq_redirect
,
"roq redirect, flush brq\n"
)
XSInfo
(
debug_brq_redirect
,
p
"brq redirect, target:${Hexadecimal(io.redirect.bits.target)} flptr:${io.redirect.bits.freelistAllocPtr}\n"
)
BoringUtils
.
addSource
(
io
.
out
.
fire
(),
"MbpInstr"
)
BoringUtils
.
addSource
(
io
.
out
.
fire
()
&&
!
commitEntry
.
misPred
,
"MbpRight"
)
BoringUtils
.
addSource
(
io
.
out
.
fire
()
&&
commitEntry
.
misPred
,
"MbpWrong"
)
BoringUtils
.
addSource
(
io
.
out
.
fire
()
&&
!
commitEntry
.
misPred
&&
commitEntry
.
exuOut
.
redirect
.
_type
===
BTBtype
.
B
,
"MbpBRight"
)
BoringUtils
.
addSource
(
io
.
out
.
fire
()
&&
commitEntry
.
misPred
&&
commitEntry
.
exuOut
.
redirect
.
_type
===
BTBtype
.
B
,
"MbpBWrong"
)
BoringUtils
.
addSource
(
io
.
out
.
fire
()
&&
!
commitEntry
.
misPred
&&
commitEntry
.
exuOut
.
redirect
.
_type
===
BTBtype
.
J
,
"MbpJRight"
)
BoringUtils
.
addSource
(
io
.
out
.
fire
()
&&
commitEntry
.
misPred
&&
commitEntry
.
exuOut
.
redirect
.
_type
===
BTBtype
.
J
,
"MbpJWrong"
)
BoringUtils
.
addSource
(
io
.
out
.
fire
()
&&
!
commitEntry
.
misPred
&&
commitEntry
.
exuOut
.
redirect
.
_type
===
BTBtype
.
I
,
"MbpIRight"
)
BoringUtils
.
addSource
(
io
.
out
.
fire
()
&&
commitEntry
.
misPred
&&
commitEntry
.
exuOut
.
redirect
.
_type
===
BTBtype
.
I
,
"MbpIWrong"
)
BoringUtils
.
addSource
(
io
.
out
.
fire
()
&&
!
commitEntry
.
misPred
&&
commitEntry
.
exuOut
.
redirect
.
_type
===
BTBtype
.
R
,
"MbpRRight"
)
BoringUtils
.
addSource
(
io
.
out
.
fire
()
&&
commitEntry
.
misPred
&&
commitEntry
.
exuOut
.
redirect
.
_type
===
BTBtype
.
R
,
"MbpRWrong"
)
}
\ No newline at end of file
src/main/scala/xiangshan/backend/roq/Roq.scala
浏览文件 @
b5f5fbe6
...
...
@@ -278,5 +278,8 @@ class Roq(implicit val p: XSConfig) extends XSModule {
debugMonitor
.
io
.
trapPC
:=
trapPC
debugMonitor
.
io
.
cycleCnt
:=
GTimer
()
debugMonitor
.
io
.
instrCnt
:=
instrCnt
// BPU temp Perf Cnt
BoringUtils
.
addSource
(
hitTrap
,
"XSTRAP_BPU"
)
}
}
src/main/scala/xiangshan/frontend/BPU.scala
浏览文件 @
b5f5fbe6
...
...
@@ -6,6 +6,8 @@ import xiangshan._
import
xiangshan.utils._
import
xiangshan.backend.ALUOpType
import
utils._
import
chisel3.util.experimental.BoringUtils
import
xiangshan.backend.decode.XSTrap
class
TableAddr
(
val
idxBits
:
Int
,
val
banks
:
Int
)
extends
XSBundle
{
def
tagBits
=
VAddrBits
-
idxBits
-
2
...
...
@@ -543,4 +545,39 @@ class BPU extends XSModule {
s3
.
io
.
predecode
<>
io
.
predecode
io
.
tageOut
<>
s3
.
io
.
out
s3
.
io
.
redirectInfo
<>
io
.
redirectInfo
// TODO: temp and ugly code, when perf counters is added( may after adding CSR), please mv the below counter
val
bpuPerfCntList
=
List
(
"MbpInstr"
,
"MbpRight"
,
"MbpWrong"
,
"MbpBRight"
,
"MbpBWrong"
,
"MbpJRight"
,
"MbpJWrong"
,
"MbpIRight"
,
"MbpIWrong"
,
"MbpRRight"
,
"MbpRWrong"
)
val
bpuPerfCnts
=
List
.
fill
(
bpuPerfCntList
.
length
)(
RegInit
(
0.
U
(
XLEN
.
W
)))
val
bpuPerfCntConds
=
List
.
fill
(
bpuPerfCntList
.
length
)(
WireInit
(
false
.
B
))
(
bpuPerfCnts
zip
bpuPerfCntConds
)
map
{
case
(
cnt
,
cond
)
=>
{
when
(
cond
)
{
cnt
:=
cnt
+
1.
U
}}}
for
(
i
<-
bpuPerfCntList
.
indices
)
{
BoringUtils
.
addSink
(
bpuPerfCntConds
(
i
),
bpuPerfCntList
(
i
))
}
val
xsTrap
=
WireInit
(
false
.
B
)
BoringUtils
.
addSink
(
xsTrap
,
"XSTRAP_BPU"
)
// if (!p.FPGAPlatform) {
when
(
xsTrap
)
{
printf
(
"=================BPU's PerfCnt================\n"
)
for
(
i
<-
bpuPerfCntList
.
indices
)
{
printf
(
bpuPerfCntList
(
i
)
+
" <- "
+
"%d\n"
,
bpuPerfCnts
(
i
))
}
}
// }
}
\ No newline at end of file
src/main/scala/xiangshan/frontend/Ibuffer.scala
浏览文件 @
b5f5fbe6
...
...
@@ -48,7 +48,7 @@ class Ibuffer extends XSModule {
val
enqValid
=
!
io
.
flush
&&
io
.
in
.
valid
&&
!
full
&&
!
ibuf_valid
(
tail_ptr
+
(
FetchWidth
*
2
).
U
)
val
deqValid
=
!
io
.
flush
&&
!
empty
//&& io.out.map(_.ready).reduce(_||_)
io
.
in
.
ready
:=
enqValid
io
.
in
.
ready
:=
!
full
&&
!
ibuf_valid
(
tail_ptr
+
(
FetchWidth
*
2
).
U
)
// enque
when
(
enqValid
)
{
...
...
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