diff --git a/src/main/scala/xiangshan/backend/brq/Brq.scala b/src/main/scala/xiangshan/backend/brq/Brq.scala
index 45f3010b4f057f4593a665100a0bdbdff5bf0974..d3bb1f85126017b431ea7bed4d31ba478cad10ef 100644
--- a/src/main/scala/xiangshan/backend/brq/Brq.scala
+++ b/src/main/scala/xiangshan/backend/brq/Brq.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.util._
 import xiangshan._
 import xiangshan.utils._
-
+import chisel3.util.experimental.BoringUtils
 
 class BrqPtr extends XSBundle {
 
@@ -221,4 +221,16 @@ class Brq extends XSModule {
 
   XSInfo(debug_roq_redirect, "roq redirect, flush brq\n")
   XSInfo(debug_brq_redirect, p"brq redirect, target:${Hexadecimal(io.redirect.bits.target)} flptr:${io.redirect.bits.freelistAllocPtr}\n")
+
+  BoringUtils.addSource(io.out.fire(), "MbpInstr")
+  BoringUtils.addSource(io.out.fire() && !commitEntry.misPred, "MbpRight")
+  BoringUtils.addSource(io.out.fire() && commitEntry.misPred, "MbpWrong")
+  BoringUtils.addSource(io.out.fire() && !commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.B, "MbpBRight")
+  BoringUtils.addSource(io.out.fire() && commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.B, "MbpBWrong")
+  BoringUtils.addSource(io.out.fire() && !commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.J, "MbpJRight")
+  BoringUtils.addSource(io.out.fire() && commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.J, "MbpJWrong")
+  BoringUtils.addSource(io.out.fire() && !commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.I, "MbpIRight")
+  BoringUtils.addSource(io.out.fire() && commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.I, "MbpIWrong")
+  BoringUtils.addSource(io.out.fire() && !commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.R, "MbpRRight")
+  BoringUtils.addSource(io.out.fire() && commitEntry.misPred && commitEntry.exuOut.redirect._type===BTBtype.R, "MbpRWrong")
 }
\ No newline at end of file
diff --git a/src/main/scala/xiangshan/backend/roq/Roq.scala b/src/main/scala/xiangshan/backend/roq/Roq.scala
index 21ba1d47d44eeb7324c1e4378eda6c360660e748..06c6585d618a97a4f12edf602932d0536de776ba 100644
--- a/src/main/scala/xiangshan/backend/roq/Roq.scala
+++ b/src/main/scala/xiangshan/backend/roq/Roq.scala
@@ -278,5 +278,8 @@ class Roq(implicit val p: XSConfig) extends XSModule {
     debugMonitor.io.trapPC := trapPC
     debugMonitor.io.cycleCnt := GTimer()
     debugMonitor.io.instrCnt := instrCnt
+
+    // BPU temp Perf Cnt
+    BoringUtils.addSource(hitTrap, "XSTRAP_BPU")
   }
 }
diff --git a/src/main/scala/xiangshan/frontend/BPU.scala b/src/main/scala/xiangshan/frontend/BPU.scala
index 768600a6aa969510a5fe867623ae5dcd77a6afad..5d6681a1d58ba2df6f59d90492fb607b2525963d 100644
--- a/src/main/scala/xiangshan/frontend/BPU.scala
+++ b/src/main/scala/xiangshan/frontend/BPU.scala
@@ -6,6 +6,8 @@ import xiangshan._
 import xiangshan.utils._
 import xiangshan.backend.ALUOpType
 import utils._
+import chisel3.util.experimental.BoringUtils
+import xiangshan.backend.decode.XSTrap
 
 class TableAddr(val idxBits: Int, val banks: Int) extends XSBundle {
   def tagBits = VAddrBits - idxBits - 2
@@ -543,4 +545,39 @@ class BPU extends XSModule {
   s3.io.predecode <> io.predecode
   io.tageOut <> s3.io.out
   s3.io.redirectInfo <> io.redirectInfo
+
+  // TODO: temp and ugly code, when perf counters is added( may after adding CSR), please mv the below counter
+  val bpuPerfCntList = List(
+    "MbpInstr",
+    "MbpRight",
+    "MbpWrong",
+    "MbpBRight",
+    "MbpBWrong",
+    "MbpJRight",
+    "MbpJWrong",
+    "MbpIRight",
+    "MbpIWrong",
+    "MbpRRight",
+    "MbpRWrong"
+  )
+
+  val bpuPerfCnts = List.fill(bpuPerfCntList.length)(RegInit(0.U(XLEN.W)))
+  val bpuPerfCntConds = List.fill(bpuPerfCntList.length)(WireInit(false.B))
+  (bpuPerfCnts zip bpuPerfCntConds) map { case (cnt, cond) => { when (cond) { cnt := cnt + 1.U }}}
+
+  for(i <- bpuPerfCntList.indices) {
+    BoringUtils.addSink(bpuPerfCntConds(i), bpuPerfCntList(i))
+  }
+
+  val xsTrap = WireInit(false.B)
+  BoringUtils.addSink(xsTrap, "XSTRAP_BPU")
+
+  // if (!p.FPGAPlatform) {
+    when (xsTrap) {
+      printf("=================BPU's PerfCnt================\n")
+      for(i <- bpuPerfCntList.indices) {
+        printf(bpuPerfCntList(i) + " <- " + "%d\n", bpuPerfCnts(i))
+      }
+    }
+  // }
 }
\ No newline at end of file
diff --git a/src/main/scala/xiangshan/frontend/Ibuffer.scala b/src/main/scala/xiangshan/frontend/Ibuffer.scala
index f73380fcfd8740959a4fc6486f5a4a2a79b6c1ae..8ba58d26e5a8b007b2359a6adab36cf4653c4635 100644
--- a/src/main/scala/xiangshan/frontend/Ibuffer.scala
+++ b/src/main/scala/xiangshan/frontend/Ibuffer.scala
@@ -48,7 +48,7 @@ class Ibuffer extends XSModule {
   val enqValid = !io.flush && io.in.valid && !full && !ibuf_valid(tail_ptr + (FetchWidth*2).U)
   val deqValid = !io.flush && !empty //&& io.out.map(_.ready).reduce(_||_)
 
-  io.in.ready := enqValid
+  io.in.ready := !full && !ibuf_valid(tail_ptr + (FetchWidth*2).U)
 
   // enque
   when(enqValid) {