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体验新版 GitCode,发现更多精彩内容 >>
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b52cb85c
编写于
10月 19, 2020
作者:
J
jinyue110
浏览文件
操作
浏览文件
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差异文件
Merge branch 'debian-gogogo' of
https://github.com/RISCVERS/XiangShan
into debian-gogogo
上级
9d4860af
289c2f50
变更
3
隐藏空白更改
内联
并排
Showing
3 changed file
with
24 addition
and
43 deletion
+24
-43
src/main/scala/xiangshan/cache/dcacheWrapper.scala
src/main/scala/xiangshan/cache/dcacheWrapper.scala
+4
-4
src/main/scala/xiangshan/cache/icache.scala
src/main/scala/xiangshan/cache/icache.scala
+4
-38
src/main/scala/xiangshan/cache/probe.scala
src/main/scala/xiangshan/cache/probe.scala
+16
-1
未找到文件。
src/main/scala/xiangshan/cache/dcacheWrapper.scala
浏览文件 @
b52cb85c
...
...
@@ -396,13 +396,13 @@ class DCacheImp(outer: DCache) extends LazyModuleImp(outer) with HasDCacheParame
// sync with prober
missQueue
.
io
.
probe_wb_req
.
valid
:=
prober
.
io
.
wb_req
.
fire
()
missQueue
.
io
.
probe_wb_req
.
bits
:=
prober
.
io
.
wb_req
.
bits
missQueue
.
io
.
probe_active
:=
prober
.
io
.
inflight_req_block_addr
missQueue
.
io
.
probe_active
:=
prober
.
io
.
probe_active
//----------------------------------------
// prober
prober
.
io
.
req
.
valid
:=
bus
.
b
.
valid
bus
.
b
.
ready
:=
prober
.
io
.
req
.
ready
&&
!
block_probe
(
get_block_addr
(
bus
.
b
.
bits
.
address
))
prober
.
io
.
req
.
bits
:=
bus
.
b
.
bits
prober
.
io
.
block
:=
block_probe
(
prober
.
io
.
inflight_req_block_addr
.
bits
)
prober
.
io
.
req
<>
bus
.
b
XSDebug
(
prober
.
io
.
block
,
"prober blocked\n"
)
//----------------------------------------
// wb
...
...
src/main/scala/xiangshan/cache/icache.scala
浏览文件 @
b52cb85c
...
...
@@ -254,14 +254,11 @@ class ICacheImp(outer: ICache) extends ICacheModule(outer)
val
s3_hit
=
RegEnable
(
next
=
s2_hit
,
init
=
false
.
B
,
enable
=
s2_fire
)
val
s3_wayMask
=
RegEnable
(
next
=
waymask
,
init
=
0.
U
,
enable
=
s2_fire
)
val
s3_miss
=
s3_valid
&&
!
s3_hit
val
s3_mmio
=
s3_valid
&&
AddressSpace
.
isMMIO
(
s3_tlb_resp
.
paddr
)
when
(
io
.
flush
(
1
))
{
s3_valid
:=
false
.
B
}
.
elsewhen
(
s2_fire
)
{
s3_valid
:=
s2_valid
}
.
elsewhen
(
io
.
resp
.
fire
())
{
s3_valid
:=
false
.
B
}
val
refillDataReg
=
Reg
(
Vec
(
refillCycles
,
UInt
(
beatBits
.
W
)))
assert
(!(
s3_hit
&&
s3_mmio
),
"MMIO address should not hit in ICache!"
)
// icache hit
// simply cut the hit cacheline
val
dataHitWay
=
s3_data
.
map
(
b
=>
Mux1H
(
s3_wayMask
,
b
).
asUInt
)
...
...
@@ -269,15 +266,10 @@ class ICacheImp(outer: ICache) extends ICacheModule(outer)
outPacket
:=
cutHelper
(
VecInit
(
dataHitWay
),
s3_req_pc
(
5
,
1
).
asUInt
,
s3_req_mask
.
asUInt
)
//icache miss
val
s_idle
::
s_m
mioReq
::
s_mmioResp
::
s_memReadReq
::
s_memReadResp
::
s_wait_resp
::
Nil
=
Enum
(
6
)
val
s_idle
::
s_m
emReadReq
::
s_memReadResp
::
s_wait_resp
::
Nil
=
Enum
(
4
)
val
state
=
RegInit
(
s_idle
)
val
readBeatCnt
=
Counter
(
refillCycles
)
//uncache request
val
mmioBeatCnt
=
Counter
(
blockWords
)
val
mmioAddrReg
=
RegInit
(
0.
U
(
PAddrBits
.
W
))
val
mmioReg
=
Reg
(
Vec
(
blockWords
/
2
,
UInt
(
blockWords
.
W
)))
//pipeline flush register
val
needFlush
=
RegInit
(
false
.
B
)
when
(
io
.
flush
(
1
)
&&
(
state
=/=
s_idle
)
&&
(
state
=/=
s_wait_resp
)){
needFlush
:=
true
.
B
}
...
...
@@ -295,35 +287,14 @@ class ICacheImp(outer: ICache) extends ICacheModule(outer)
// state change to wait for a cacheline refill
val
countFull
=
readBeatCnt
.
value
===
(
refillCycles
-
1
).
U
val
mmioCntFull
=
mmioBeatCnt
.
value
===
(
blockWords
-
1
).
U
switch
(
state
){
is
(
s_idle
){
when
(
s3_mmio
&&
io
.
flush
===
0.
U
){
state
:=
s_mmioReq
mmioBeatCnt
.
value
:=
0.
U
mmioAddrReg
:=
s3_tlb_resp
.
paddr
}
.
elsewhen
(
s3_miss
&&
io
.
flush
===
0.
U
){
when
(
s3_miss
&&
io
.
flush
===
0.
U
){
state
:=
s_memReadReq
readBeatCnt
.
value
:=
0.
U
}
}
//mmio request
is
(
s_mmioReq
){
when
(
bus
.
a
.
fire
()){
state
:=
s_mmioResp
mmioAddrReg
:=
mmioAddrReg
+
8.
U
//consider MMIO response 64 bits valid data
}
}
is
(
s_mmioResp
){
when
(
edge
.
hasData
(
bus
.
d
.
bits
)
&&
bus
.
d
.
fire
())
{
mmioBeatCnt
.
inc
()
assert
(
refill_done
,
"MMIO response should be one beat only!"
)
mmioReg
(
mmioBeatCnt
.
value
)
:=
bus
.
d
.
bits
.
data
(
wordBits
-
1
,
0
)
state
:=
Mux
(
mmioCntFull
,
s_wait_resp
,
s_mmioReq
)
}
}
// memory request
is
(
s_memReadReq
){
...
...
@@ -355,7 +326,6 @@ class ICacheImp(outer: ICache) extends ICacheModule(outer)
val
refillFinalOneBeat
=
(
state
===
s_memReadResp
)
&&
bus
.
d
.
fire
()
&&
refill_done
val
wayNum
=
OHToUInt
(
s3_wayMask
.
asTypeOf
(
Vec
(
nWays
,
Bool
())))
val
validPtr
=
Cat
(
get_idx
(
s3_req_pc
),
wayNum
)
//metaWrite.tag := get_tag(s3_req_pc)
metaWrite
.
tag
:=
s3_tag
metaArray
.
io
.
w
.
req
.
valid
:=
refillFinalOneBeat
metaArray
.
io
.
w
.
req
.
bits
.
apply
(
data
=
metaWrite
,
setIdx
=
get_idx
(
s3_req_pc
),
waymask
=
s3_wayMask
)
...
...
@@ -446,16 +416,12 @@ class ICacheImp(outer: ICache) extends ICacheModule(outer)
bus
.
b
.
ready
:=
true
.
B
bus
.
c
.
valid
:=
false
.
B
bus
.
e
.
valid
:=
false
.
B
bus
.
a
.
valid
:=
(
state
===
s_memReadReq
)
||
(
state
===
s_mmioReq
)
bus
.
a
.
valid
:=
(
state
===
s_memReadReq
)
val
memTileReq
=
edge
.
Get
(
fromSource
=
cacheID
.
U
,
toAddress
=
groupPC
(
s3_tlb_resp
.
paddr
),
lgSize
=
(
log2Up
(
cacheParams
.
blockBytes
)).
U
).
_2
val
mmioTileReq
=
edge
.
Get
(
fromSource
=
cacheID
.
U
,
toAddress
=
mmioAddrReg
,
lgSize
=
(
log2Up
(
wordBits
)).
U
).
_2
bus
.
a
.
bits
:=
Mux
((
state
===
s_mmioReq
),
mmioTileReq
,
memTileReq
)
bus
.
a
.
bits
:=
memTileReq
bus
.
d
.
ready
:=
true
.
B
XSDebug
(
"[flush] flush_0:%d flush_1:%d\n"
,
io
.
flush
(
0
),
io
.
flush
(
1
))
...
...
src/main/scala/xiangshan/cache/probe.scala
浏览文件 @
b52cb85c
...
...
@@ -16,11 +16,13 @@ class ProbeUnit(edge: TLEdgeOut) extends DCacheModule with HasTLDump {
val
meta_write
=
Decoupled
(
new
L1MetaWriteReq
)
val
wb_req
=
Decoupled
(
new
WritebackReq
(
edge
.
bundle
.
sourceBits
))
val
wb_resp
=
Input
(
Bool
())
val
block
=
Input
(
Bool
())
val
inflight_req_idx
=
Output
(
Valid
(
UInt
()))
val
inflight_req_block_addr
=
Output
(
Valid
(
UInt
()))
val
probe_active
=
Output
(
Valid
(
UInt
()))
})
val
s_invalid
::
s_
meta_read_req
::
s_meta_read_resp
::
s_decide_next_state
::
s_release
::
s_wb_req
::
s_wb_resp
::
s_meta_write_req
::
Nil
=
Enum
(
8
)
val
s_invalid
::
s_
wait_sync
::
s_meta_read_req
::
s_meta_read_resp
::
s_decide_next_state
::
s_release
::
s_wb_req
::
s_wb_resp
::
s_meta_write_req
::
Nil
=
Enum
(
9
)
val
state
=
RegInit
(
s_invalid
)
...
...
@@ -53,12 +55,25 @@ class ProbeUnit(edge: TLEdgeOut) extends DCacheModule with HasTLDump {
io
.
inflight_req_block_addr
.
valid
:=
state
=/=
s_invalid
io
.
inflight_req_block_addr
.
bits
:=
req_block_addr
// active means nobody is blocking it anymore
// it will run free
io
.
probe_active
.
valid
:=
state
=/=
s_invalid
&&
state
=/=
s_wait_sync
io
.
probe_active
.
bits
:=
req_idx
XSDebug
(
"state: %d\n"
,
state
)
when
(
state
===
s_invalid
)
{
io
.
req
.
ready
:=
true
.
B
when
(
io
.
req
.
fire
())
{
req
:=
io
.
req
.
bits
state
:=
s_wait_sync
}
}
// we could be blocked by miss queue, or anything else
// just wait for them
when
(
state
===
s_wait_sync
)
{
when
(!
io
.
block
)
{
state
:=
s_meta_read_req
}
}
...
...
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