Merge pull request #163 from RISCVERS/opt-pipeline

Optimize pipeline

src/main/scala/xiangshan/Bundle.scala

@@ -25,7 +25,7 @@ class FetchPacket extends XSBundle {
 
 class ValidUndirectioned[T <: Data](gen: T) extends Bundle {
   val valid = Bool()
-  val bits = gen.asInstanceOf[T]
+  val bits = gen.cloneType.asInstanceOf[T]
   override def cloneType = new ValidUndirectioned(gen).asInstanceOf[this.type]
 }
 

src/main/scala/xiangshan/backend/Backend.scala

@@ -15,7 +15,7 @@ import xiangshan.backend.fu.FunctionUnit
 import xiangshan.backend.issue.IssueQueue
 import xiangshan.backend.regfile.{Regfile, RfWritePort}
 import xiangshan.backend.roq.Roq
-
+import utils.ParallelOR
 
 /** Backend Pipeline:
   * Decode -> Rename -> Dispatch-1 -> Dispatch-2 -> Issue -> Exe
@@ -137,6 +137,7 @@ class Backend(implicit val p: XSConfig) extends XSModule
     x.valid := y.io.out.fire() && y.io.out.bits.redirectValid
   }
   decode.io.brTags <> brq.io.brTags
+  decBuf.io.isWalking := ParallelOR(roq.io.commits.map(c => c.valid && c.bits.isWalk)).asBool() // TODO: opt this
   decBuf.io.redirect <> redirect
   decBuf.io.in <> decode.io.out
 

src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala

@@ -7,6 +7,7 @@ import utils._
 
 class DecodeBuffer extends XSModule {
   val io = IO(new Bundle() {
+    val isWalking = Input(Bool())
     val redirect = Flipped(ValidIO(new Redirect))
     val in  = Vec(DecodeWidth, Flipped(DecoupledIO(new CfCtrl)))
     val out = Vec(RenameWidth, DecoupledIO(new CfCtrl))
@@ -44,10 +45,10 @@ class DecodeBuffer extends XSModule {
         Mux(r.ctrl.noSpecExec,
           !ParallelOR(validVec.take(i)).asBool(),
           !ParallelOR(io.out.zip(validVec).take(i).map(x => x._2 && x._1.bits.ctrl.noSpecExec)).asBool()
-        )
+        ) && !io.isWalking
     } else {
       require( i == 0)
-      io.out(i).valid := validVec(i) && !io.redirect.valid
+      io.out(i).valid := validVec(i) && !io.redirect.valid && !io.isWalking
     }
   }
 

src/main/scala/xiangshan/backend/rename/Rename.scala

@@ -21,15 +21,9 @@ class Rename extends XSModule {
     val out = Vec(RenameWidth, DecoupledIO(new MicroOp))
   })
 
-  val isWalk = ParallelOR(io.roqCommits.map(x => x.valid && x.bits.isWalk)).asBool()
-
-  val debug_exception = io.redirect.valid && io.redirect.bits.isException
-  val debug_walk = isWalk
-  val debug_norm = !(debug_exception || debug_walk)
-
   def printRenameInfo(in: DecoupledIO[CfCtrl], out: DecoupledIO[MicroOp]) = {
     XSInfo(
-      debug_norm && in.valid && in.ready,
+      in.valid && in.ready,
       p"pc:${Hexadecimal(in.bits.cf.pc)} in v:${in.valid} in rdy:${in.ready} " +
         p"lsrc1:${in.bits.ctrl.lsrc1} -> psrc1:${out.bits.psrc1} " +
         p"lsrc2:${in.bits.ctrl.lsrc2} -> psrc2:${out.bits.psrc2} " +
@@ -73,19 +67,22 @@ class Rename extends XSModule {
     uop.roqIdx := DontCare
   })
 
-  var lastReady = WireInit(true.B)
+  var lastReady = WireInit(io.out(0).ready)
+  // debug assert
+  val outRdy = Cat(io.out.map(_.ready))
+  assert(outRdy===0.U || outRdy.andR())
   for(i <- 0 until RenameWidth) {
     uops(i).cf := io.in(i).bits.cf
     uops(i).ctrl := io.in(i).bits.ctrl
     uops(i).brTag := io.in(i).bits.brTag
 
-    val inValid = io.in(i).valid && !isWalk
+    val inValid = io.in(i).valid
 
     // alloc a new phy reg
     val needFpDest = inValid && needDestReg(fp = true, io.in(i).bits)
     val needIntDest = inValid && needDestReg(fp = false, io.in(i).bits)
-    fpFreeList.allocReqs(i) := needFpDest && lastReady && io.out(i).ready
-    intFreeList.allocReqs(i) := needIntDest && lastReady && io.out(i).ready
+    fpFreeList.allocReqs(i) := needFpDest && lastReady
+    intFreeList.allocReqs(i) := needIntDest && lastReady
     val fpCanAlloc = fpFreeList.canAlloc(i)
     val intCanAlloc = intFreeList.canAlloc(i)
     val this_can_alloc = Mux(
@@ -97,7 +94,7 @@ class Rename extends XSModule {
         true.B
       )
     )
-    io.in(i).ready := lastReady && io.out(i).ready && this_can_alloc && !isWalk
+    io.in(i).ready := lastReady && this_can_alloc
 
     // do checkpoints when a branch inst come
     for(fl <- Seq(fpFreeList, intFreeList)){