dcache: fix fanout

* pipelineReg in miss queue
* translated_cache_req_opCode and io_cache_req_valid_reg in cacheOpDecoder
* r_way_en_reg in bankedDataArray

src/main/scala/xiangshan/cache/CacheInstruction.scala

@@ -141,6 +141,7 @@ class CSRCacheOpDecoder(decoder_name: String, id: Int)(implicit p: Parameters) e
   val io = IO(new Bundle {
     val csr = new L1CacheToCsrIO
     val cache = new L1CacheInnerOpIO
+    val cache_req_dup_0 = Valid(new CacheCtrlReqInfo)
     val error = Flipped(new L1CacheErrorInfo)
   })
 
@@ -154,7 +155,8 @@ class CSRCacheOpDecoder(decoder_name: String, id: Int)(implicit p: Parameters) e
   val data_transfer_cnt = RegInit(0.U(log2Up(maxDataRowSupport).W))
 
   // Translate CSR write to cache op
-  val translated_cache_req                  = RegInit(0.U.asTypeOf(new CacheCtrlReqInfo))
+  val translated_cache_req = Reg(new CacheCtrlReqInfo)
+  val translated_cache_req_opCode_dup_0 = Reg(UInt(XLEN.W))
   println("Cache op decoder (" + decoder_name + "):")
   println("  Id " + id)
   // CacheInsRegisterList.map{case (name, attribute) => {
@@ -176,6 +178,7 @@ class CSRCacheOpDecoder(decoder_name: String, id: Int)(implicit p: Parameters) e
   }
 
   update_cache_req_when_write("CACHE_OP", translated_cache_req.opCode)
+  update_cache_req_when_write("CACHE_OP", translated_cache_req_opCode_dup_0)
   update_cache_req_when_write("CACHE_LEVEL", translated_cache_req.level)
   update_cache_req_when_write("CACHE_WAY", translated_cache_req.wayNum)
   update_cache_req_when_write("CACHE_IDX", translated_cache_req.index)
@@ -200,7 +203,9 @@ class CSRCacheOpDecoder(decoder_name: String, id: Int)(implicit p: Parameters) e
 
   // Send cache op to cache
   io.cache.req.valid := RegNext(cache_op_start)
+  io.cache_req_dup_0.valid := RegNext(cache_op_start)
   io.cache.req.bits := translated_cache_req
+  io.cache_req_dup_0.bits := translated_cache_req
   when(io.cache.req.fire()){
     wait_cache_op_resp := true.B
   }
@@ -233,8 +238,8 @@ class CSRCacheOpDecoder(decoder_name: String, id: Int)(implicit p: Parameters) e
   io.csr.update.w.valid := schedule_csr_op_resp_data || schedule_csr_op_resp_finish
   io.csr.update.w.bits := DontCare
 
-  val isReadTagECC = WireInit(CacheInstrucion.isReadTagECC(translated_cache_req.opCode))
-  val isReadDataECC = WireInit(CacheInstrucion.isReadDataECC(translated_cache_req.opCode))
+  val isReadTagECC = WireInit(CacheInstrucion.isReadTagECC(translated_cache_req_opCode_dup_0))
+  val isReadDataECC = WireInit(CacheInstrucion.isReadDataECC(translated_cache_req_opCode_dup_0))
   val isReadTag = WireInit(CacheInstrucion.isReadTag(translated_cache_req.opCode))
   val isReadData = WireInit(CacheInstrucion.isReadData(translated_cache_req.opCode))
 

src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala

@@ -186,6 +186,22 @@ trait HasDCacheParameters extends HasL1CacheParameters {
     AddPipelineReg(arb.io.out, out, false.B)
   }
 
+  def arbiter_with_pipereg_N_dup[T <: Bundle](
+    in: Seq[DecoupledIO[T]],
+    out: DecoupledIO[T],
+    dups: Seq[T],
+    name: Option[String] = None): Unit = {
+    val arb = Module(new Arbiter[T](chiselTypeOf(out.bits), in.size))
+    if (name.nonEmpty) { arb.suggestName(s"${name.get}_arb") }
+    for ((a, req) <- arb.io.in.zip(in)) {
+      a <> req
+    }
+    AddPipelineReg(arb.io.out, out, false.B)
+    for (dup <- dups) {
+      dup := RegEnable(arb.io.out.bits, arb.io.out.fire())
+    }
+  }
+
   def rrArbiter[T <: Bundle](
     in: Seq[DecoupledIO[T]],
     out: DecoupledIO[T],
@@ -644,6 +660,10 @@ class DCacheImp(outer: DCache) extends LazyModuleImp(outer) with HasDCacheParame
         s.bits.way_en === missQueue.io.refill_pipe_req.bits.way_en
     )).orR
   block_decoupled(missQueue.io.refill_pipe_req, refillPipe.io.req, refillShouldBeBlocked)
+  refillPipe.io.req_dup_0 := missQueue.io.refill_pipe_req_dup_0
+  refillPipe.io.req_dup_1 := missQueue.io.refill_pipe_req_dup_1
+  refillPipe.io.req_dup_2 := missQueue.io.refill_pipe_req_dup_2
+  refillPipe.io.req_dup_3 := missQueue.io.refill_pipe_req_dup_3
   missQueue.io.refill_pipe_resp := refillPipe.io.resp
   io.lsu.store.refill_hit_resp := RegNext(refillPipe.io.store_resp)
 
@@ -729,7 +749,7 @@ class DCacheImp(outer: DCache) extends LazyModuleImp(outer) with HasDCacheParame
   // Customized csr cache op support
   val cacheOpDecoder = Module(new CSRCacheOpDecoder("dcache", CacheInstrucion.COP_ID_DCACHE))
   cacheOpDecoder.io.csr <> io.csr
-  bankedDataArray.io.cacheOp.req := cacheOpDecoder.io.cache.req
+  bankedDataArray.io.cacheOp.req := cacheOpDecoder.io.cache_req_dup_0
   tagArray.io.cacheOp.req := cacheOpDecoder.io.cache.req
   cacheOpDecoder.io.cache.resp.valid := bankedDataArray.io.cacheOp.resp.valid ||
     tagArray.io.cacheOp.resp.valid

src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala

@@ -158,6 +158,7 @@ class BankedDataArray(implicit p: Parameters) extends AbstractBankedDataArray {
     })
 
     val r_way_en_reg = RegNext(io.r.way_en)
+    val r_way_en_reg_dup_0 = RegNext(io.r.way_en)
 
     // multiway data bank
     val data_bank = Array.fill(DCacheWays) {
@@ -186,7 +187,7 @@ class BankedDataArray(implicit p: Parameters) extends AbstractBankedDataArray {
     val half = nWays / 2
     val data_read = data_bank.map(_.io.r.resp.data(0))
     val data_left = Mux1H(r_way_en_reg.tail(half), data_read.take(half))
-    val data_right = Mux1H(r_way_en_reg.head(half), data_read.drop(half))
+    val data_right = Mux1H(r_way_en_reg_dup_0.head(half), data_read.drop(half))
 
     val sel_low = r_way_en_reg.tail(half).orR()
     val row_data = Mux(sel_low, data_left, data_right)

src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala

@@ -542,6 +542,10 @@ class MissQueue(edge: TLEdgeOut)(implicit p: Parameters) extends DCacheModule wi
     val mem_finish = DecoupledIO(new TLBundleE(edge.bundle))
 
     val refill_pipe_req = DecoupledIO(new RefillPipeReq)
+    val refill_pipe_req_dup_0 = Output(new RefillPipeReq)
+    val refill_pipe_req_dup_1 = Output(new RefillPipeReq)
+    val refill_pipe_req_dup_2 = Output(new RefillPipeReq)
+    val refill_pipe_req_dup_3 = Output(new RefillPipeReq)
     val refill_pipe_resp = Flipped(ValidIO(UInt(log2Up(cfg.nMissEntries).W)))
 
     val replace_pipe_req = DecoupledIO(new MainPipeReq)
@@ -642,7 +646,9 @@ class MissQueue(edge: TLEdgeOut)(implicit p: Parameters) extends DCacheModule wi
   TLArbiter.lowest(edge, io.mem_acquire, entries.map(_.io.mem_acquire):_*)
   TLArbiter.lowest(edge, io.mem_finish, entries.map(_.io.mem_finish):_*)
 
-  arbiter_with_pipereg(entries.map(_.io.refill_pipe_req), io.refill_pipe_req, Some("refill_pipe_req"))
+  arbiter_with_pipereg_N_dup(entries.map(_.io.refill_pipe_req), io.refill_pipe_req, 
+  dups=Seq(io.refill_pipe_req_dup_0, io.refill_pipe_req_dup_1, io.refill_pipe_req_dup_2, io.refill_pipe_req_dup_3), 
+  Some("refill_pipe_req"))
 
   arbiter_with_pipereg(entries.map(_.io.replace_pipe_req), io.replace_pipe_req, Some("replace_pipe_req"))
 

src/main/scala/xiangshan/cache/dcache/mainpipe/RefillPipe.scala

@@ -43,6 +43,10 @@ class RefillPipeReq(implicit p: Parameters) extends DCacheBundle {
 class RefillPipe(implicit p: Parameters) extends DCacheModule {
   val io = IO(new Bundle() {
     val req = Flipped(DecoupledIO(new RefillPipeReq))
+    val req_dup_0 = Input(new RefillPipeReq)
+    val req_dup_1 = Input(new RefillPipeReq)
+    val req_dup_2 = Input(new RefillPipeReq)
+    val req_dup_3 = Input(new RefillPipeReq)
     val resp = ValidIO(UInt(log2Up(cfg.nMissEntries).W))
 
     val data_write = DecoupledIO(new L1BankedDataWriteReq)
@@ -61,6 +65,11 @@ class RefillPipe(implicit p: Parameters) extends DCacheModule {
   val refill_w_valid = io.req.valid
   val refill_w_req = io.req.bits
 
+  val req_dup_0 = io.req_dup_0
+  val req_dup_1 = io.req_dup_1
+  val req_dup_2 = io.req_dup_2
+  val req_dup_3 = io.req_dup_3
+
   io.req.ready := true.B
   io.resp.valid := io.req.fire()
   io.resp.bits := refill_w_req.miss_id
@@ -69,24 +78,24 @@ class RefillPipe(implicit p: Parameters) extends DCacheModule {
   val tag = get_tag(refill_w_req.addr)
 
   io.data_write.valid := refill_w_valid
-  io.data_write.bits.addr := refill_w_req.paddrWithVirtualAlias
-  io.data_write.bits.way_en := refill_w_req.way_en
+  io.data_write.bits.addr := req_dup_0.paddrWithVirtualAlias
+  io.data_write.bits.way_en := req_dup_0.way_en
   io.data_write.bits.wmask := refill_w_req.wmask
   io.data_write.bits.data := refill_w_req.data
 
   io.meta_write.valid := refill_w_valid
-  io.meta_write.bits.idx := idx
-  io.meta_write.bits.way_en := refill_w_req.way_en
+  io.meta_write.bits.idx := req_dup_1.idx
+  io.meta_write.bits.way_en := req_dup_1.way_en
   io.meta_write.bits.meta := refill_w_req.meta
 
   io.error_flag_write.valid := refill_w_valid
-  io.error_flag_write.bits.idx := idx
-  io.error_flag_write.bits.way_en := refill_w_req.way_en
+  io.error_flag_write.bits.idx := req_dup_2.idx
+  io.error_flag_write.bits.way_en := req_dup_2.way_en
   io.error_flag_write.bits.error := refill_w_req.error
 
   io.tag_write.valid := refill_w_valid
-  io.tag_write.bits.idx := idx
-  io.tag_write.bits.way_en := refill_w_req.way_en
+  io.tag_write.bits.idx := req_dup_3.idx
+  io.tag_write.bits.way_en := req_dup_3.way_en
   io.tag_write.bits.tag := tag
 
   io.store_resp.valid := refill_w_valid && refill_w_req.source === STORE_SOURCE.U