noop,CSR: add instruction type counters

src/main/scala/noop/CSR.scala

@@ -40,6 +40,11 @@ trait HasCSRConst {
   val Minstreth     = 0xb82
 
   val MImemStall  = 0xb03
+  val MALUInstr   = 0xb04
+  val MBRUInstr   = 0xb05
+  val MLSUInstr   = 0xb06
+  val MMDUInstr   = 0xb07
+  val MCSRInstr   = 0xb08
 
   def privEcall = 0x000.U
   def privMret  = 0x302.U

src/main/scala/noop/Decode.scala

@@ -37,7 +37,7 @@ trait HasFuType
     with HasLSUOpType
     with HasMDUOpType
     with HasCSROpType {
-  private val FuTypeNum = 5
+  val FuTypeNum = 5
   def FuAlu = "b000".U
   def FuBru = "b001".U
   def FuLsu = "b010".U

src/main/scala/noop/EXU.scala

@@ -15,35 +15,39 @@ class EXU extends Module with HasFuType {
     val csr = new Bundle {
       val isCsr = Output(Bool())
       val in = Flipped(Decoupled(UInt(32.W)))
+      val instrType = Vec(FuTypeNum, Output(Bool()))
     }
   })
 
   val (src1, src2, fuType, fuOpType) = (io.in.bits.data.src1, io.in.bits.data.src2,
     io.in.bits.ctrl.fuType, io.in.bits.ctrl.fuOpType)
 
+  val fuValids = Wire(Vec(FuTypeNum, Bool()))
+  (0 until FuTypeNum).map (i => fuValids(i) := (fuType === i.U) && io.in.valid)
+
   val alu = Module(new ALU)
-  val aluOut = alu.access(valid = (fuType === FuAlu), src1 = src1, src2 = src2, func = fuOpType)
+  val aluOut = alu.access(valid = fuValids(FuAlu), src1 = src1, src2 = src2, func = fuOpType)
   alu.io.out.ready := true.B
 
   val bru = Module(new BRU)
-  val bruOut = bru.access(valid = (fuType === FuBru), src1 = src1, src2 = io.in.bits.data.dest, func = fuOpType)
+  val bruOut = bru.access(valid = fuValids(FuBru), src1 = src1, src2 = io.in.bits.data.dest, func = fuOpType)
   bru.io.pc := io.in.bits.pc
   bru.io.offset := src2
   io.br <> bru.io.branch
   bru.io.out.ready := true.B
 
   val lsu = Module(new LSU)
-  val lsuOut = lsu.access(valid = (fuType === FuLsu), src1 = src1, src2 = src2, func = fuOpType)
+  val lsuOut = lsu.access(valid = fuValids(FuLsu), src1 = src1, src2 = src2, func = fuOpType)
   lsu.io.wdata := io.in.bits.data.dest
   io.dmem <> lsu.io.dmem
   lsu.io.out.ready := true.B
 
   val mdu = Module(new MDU)
-  val mduOut = mdu.access(valid = (fuType === FuMdu), src1 = src1, src2 = src2, func = fuOpType)
+  val mduOut = mdu.access(valid = fuValids(FuMdu), src1 = src1, src2 = src2, func = fuOpType)
   mdu.io.out.ready := true.B
 
   // CSR is instantiated under NOOP
-  io.csr.isCsr := fuType === FuCsr
+  io.csr.isCsr := fuValids(FuCsr)
   io.csr.in.ready := true.B
 
   io.out.bits.data := DontCare
@@ -65,4 +69,11 @@ class EXU extends Module with HasFuType {
     FuLsu -> lsu.io.out.valid,
     FuMdu -> mdu.io.out.valid
   ))
+
+  // perfcnt
+  io.csr.instrType(FuAlu) := alu.io.out.fire()
+  io.csr.instrType(FuBru) := bru.io.out.fire()
+  io.csr.instrType(FuLsu) := lsu.io.out.fire()
+  io.csr.instrType(FuMdu) := mdu.io.out.fire()
+  io.csr.instrType(FuCsr) := io.csr.isCsr && io.csr.in.ready
 }

src/main/scala/noop/NOOP.scala

@@ -10,7 +10,7 @@ trait NOOPConfig {
   val HasMExtension = true
 }
 
-class NOOP extends Module with NOOPConfig with HasCSRConst {
+class NOOP extends Module with NOOPConfig with HasCSRConst with HasFuType {
   val io = IO(new Bundle {
     val imem = new MemIO
     val dmem = new MemIO
@@ -64,6 +64,11 @@ class NOOP extends Module with NOOPConfig with HasCSRConst {
   csr.setPerfCnt(Mcycle, true.B)
   csr.setPerfCnt(Minstret, wbu.io.writeback)
   csr.setPerfCnt(MImemStall, ifu.io.imemStall)
+  csr.setPerfCnt(MALUInstr, exu.io.csr.instrType(FuAlu))
+  csr.setPerfCnt(MBRUInstr, exu.io.csr.instrType(FuBru))
+  csr.setPerfCnt(MLSUInstr, exu.io.csr.instrType(FuLsu))
+  csr.setPerfCnt(MMDUInstr, exu.io.csr.instrType(FuMdu))
+  csr.setPerfCnt(MCSRInstr, exu.io.csr.instrType(FuCsr))
 
   io.trap := isu.io.trap
   io.sim <> csr.io.sim