IFU: if1_valid in 0~501

src/main/scala/xiangshan/XSCore.scala

@@ -26,7 +26,7 @@ trait HasXSParameter {
   val DataBytes = DataBits / 8
   val HasFPU = true
   val FetchWidth = 8
-  val EnableBPU = false
+  val EnableBPU = true
   val EnableBPD = true // enable backing predictor(like Tage) in BPUStage3
   val HistoryLength = 64
   val BtbSize = 128

src/main/scala/xiangshan/frontend/IFU.scala

@@ -8,7 +8,6 @@ import xiangshan.utils._
 
 trait HasIFUConst { this: XSModule =>
   val resetVector = 0x80000000L//TODO: set reset vec
-  val enableBPU = false
   val groupAlign = log2Up(FetchWidth * 4)
   def groupPC(pc: UInt): UInt = Cat(pc(VAddrBits-1, groupAlign), 0.U(groupAlign.W))
   
@@ -48,7 +47,7 @@ class IFU extends XSModule with HasIFUConst
     //-------------------------
     //local
     val if1_npc = WireInit(0.U(VAddrBits.W))
-    val if1_valid = !reset.asBool  && (GTimer() > 500.U)//TODO:this is ugly
+    val if1_valid = !reset.asBool 
     val if1_pc = RegInit(resetVector.U(VAddrBits.W))
     //next
     val if2_ready = WireInit(false.B)
@@ -63,8 +62,6 @@ class IFU extends XSModule with HasIFUConst
     //when((GTimer() === 501.U)){ //TODO:this is ugly
       XSDebug("RESET....\n")
       if1_npc := resetVector.U(VAddrBits.W)
-    } .elsewhen(GTimer() === 501.U){ //TODO: this may cause bug
-      if1_npc := resetVector.U(VAddrBits.W)
     } .otherwise{
       if1_npc := if2_snpc
     }
@@ -170,10 +167,10 @@ class IFU extends XSModule with HasIFUConst
 
     //Output -> iBuffer
     //io.fetchPacket <> DontCare
-    if4_ready := io.fetchPacket.ready && (io.icacheResp.valid || !if4_valid)
+    if4_ready := io.fetchPacket.ready && (io.icacheResp.valid || !if4_valid) && (GTimer() > 500.U)
     io.fetchPacket.valid := if4_valid && !io.redirectInfo.flush()
     io.fetchPacket.bits.instrs := io.icacheResp.bits.icacheOut
-    if(enableBPU){
+    if(EnableBPU){
       io.fetchPacket.bits.mask := Mux( if4_tage_taken,
         (Fill(FetchWidth*2, 1.U(1.W)) & Cat(if4_tage_insMask.map(i => Fill(2, i.asUInt))).asUInt) << if4_pc(2+log2Up(FetchWidth)-1, 1),
         Fill(FetchWidth*2, 1.U(1.W)) << if4_pc(2+log2Up(FetchWidth)-1, 1)
@@ -211,7 +208,7 @@ class IFU extends XSModule with HasIFUConst
 
     bpu.io.redirectInfo := io.redirectInfo
 
-    io.icacheResp.ready := io.fetchPacket.ready 
+    io.icacheResp.ready := io.fetchPacket.ready && (GTimer() > 500.U)
 
 }