AXI4RAM: fixed rIdx and wIdx.

Now, we can pass coremark.

src/main/scala/device/AXI4RAM.scala

@@ -52,8 +52,8 @@ class AXI4RAM
       val mems = (0 until split).map {_ => Module(new RAMHelper(bankByte))}
       mems.zipWithIndex map { case (mem, i) =>
         mem.io.clk := clock
-        mem.io.rIdx := rIdx
-        mem.io.wIdx := wIdx
+        mem.io.rIdx := (rIdx << log2Up(split)) + i.U
+        mem.io.wIdx := (wIdx << log2Up(split)) + i.U
         mem.io.wdata := in.w.bits.data((i + 1) * 64 - 1, i * 64)
         mem.io.wmask := MaskExpand(in.w.bits.strb((i + 1) * 8 - 1, i * 8))
         mem.io.wen := wen