LSQ: opt lsIdx allocate timing

src/main/scala/xiangshan/mem/lsqueue/separated/LSQWrapper.scala

@@ -139,11 +139,12 @@ class LsqWrappper extends XSModule with HasDCacheParameters {
     // fix valid, allocate lq / sq index
     (0 until RenameWidth).map(i => {
       val isStore = CommitType.lsInstIsStore(io.dp1Req(i).bits.ctrl.commitType)
-      val prevCanIn = if (i == 0) true.B else Cat((0 until i).map(i => io.dp1Req(i).ready)).andR
-      loadQueue.io.dp1Req(i).valid := !isStore && io.dp1Req(i).valid && prevCanIn
-      storeQueue.io.dp1Req(i).valid := isStore && io.dp1Req(i).valid && prevCanIn
+      loadQueue.io.dp1Req(i).valid := !isStore && io.dp1Req(i).valid
+      storeQueue.io.dp1Req(i).valid := isStore && io.dp1Req(i).valid
       loadQueue.io.lqIdxs(i) <> io.lsIdxs(i).lqIdx
       storeQueue.io.sqIdxs(i) <> io.lsIdxs(i).sqIdx
+      loadQueue.io.lqReady <> storeQueue.io.lqReady
+      loadQueue.io.sqReady <> storeQueue.io.sqReady
       io.lsIdxs(i).lsroqIdx := DontCare
       io.dp1Req(i).ready := storeQueue.io.dp1Req(i).ready && loadQueue.io.dp1Req(i).ready
     })

src/main/scala/xiangshan/mem/lsqueue/separated/LoadQueue.scala

@@ -28,6 +28,8 @@ object LqPtr extends HasXSParameter {
 class LoadQueue extends XSModule with HasDCacheParameters with HasCircularQueuePtrHelper {
   val io = IO(new Bundle() {
     val dp1Req = Vec(RenameWidth, Flipped(DecoupledIO(new MicroOp)))
+    val lqReady = Output(Vec(RenameWidth, Bool()))
+    val sqReady = Input(Vec(RenameWidth, Bool()))
     val lqIdxs = Output(Vec(RenameWidth, new LqPtr)) // LSIdx will be assembled in LSQWrapper
     val brqRedirect = Input(Valid(new Redirect))
     val loadIn = Vec(LoadPipelineWidth, Flipped(Valid(new LsPipelineBundle)))
@@ -91,7 +93,8 @@ class LoadQueue extends XSModule with HasDCacheParameters with HasCircularQueueP
       // data(index).bwdMask := 0.U(8.W).asBools
     }
     val numTryEnqueue = offset +& io.dp1Req(i).valid
-    io.dp1Req(i).ready := numTryEnqueue <= emptyEntries
+    io.lqReady(i) := numTryEnqueue <= emptyEntries
+    io.dp1Req(i).ready := io.lqReady(i) &* io.sqReady(i)
     io.lqIdxs(i) := lqIdx
     XSDebug(false, true.B, "(%d, %d) ", io.dp1Req(i).ready, io.dp1Req(i).valid)
   }

src/main/scala/xiangshan/mem/lsqueue/separated/StoreQueue.scala

@@ -25,6 +25,8 @@ object SqPtr extends HasXSParameter {
 class StoreQueue extends XSModule with HasDCacheParameters with HasCircularQueuePtrHelper {
   val io = IO(new Bundle() {
     val dp1Req = Vec(RenameWidth, Flipped(DecoupledIO(new MicroOp)))
+    val lqReady = Input(Vec(RenameWidth, Bool()))
+    val sqReady = Output(Vec(RenameWidth, Bool()))
     val sqIdxs = Output(Vec(RenameWidth, new SqPtr))
     val brqRedirect = Input(Valid(new Redirect))
     val storeIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle)))
@@ -87,7 +89,8 @@ class StoreQueue extends XSModule with HasDCacheParameters with HasCircularQueue
       // data(index).bwdMask := 0.U(8.W).asBools
     }
     val numTryEnqueue = offset +& io.dp1Req(i).valid
-    io.dp1Req(i).ready := numTryEnqueue <= emptyEntries
+    io.sqReady(i) := numTryEnqueue <= emptyEntries
+    io.dp1Req(i).ready := io.lqReady(i) && io.sqReady(i)
     io.sqIdxs(i) := sqIdx
     XSDebug(false, true.B, "(%d, %d) ", io.dp1Req(i).ready, io.dp1Req(i).valid)
   }

src/main/scala/xiangshan/mem/lsqueue/unified/Lsroq.scala

@@ -13,7 +13,6 @@ import xiangshan.backend.roq.RoqPtr
 class LsRoqEntry extends XSBundle {
   val vaddr = UInt(VAddrBits.W) // TODO: need opt
   val paddr = UInt(PAddrBits.W)
-  val op = UInt(6.W)
   val mask = UInt(8.W)
   val data = UInt(XLEN.W)
   val exception = UInt(16.W) // TODO: opt size