L1DCache: added some debug logs.

src/main/scala/xiangshan/cache/DCacheWrapper.scala

@@ -148,7 +148,7 @@ class DCacheImp(outer: DCache) extends LazyModuleImp(outer) with HasDCacheParame
   val storeReplayUnit = Module(new StoreReplayQueue)
   val atomicsReplayUnit = Module(new AtomicsReplayEntry)
 
-  val mainPipe  = Module(new MainPipe)
+  val mainPipe   = Module(new MainPipe)
   val missQueue  = Module(new MissQueue(edge))
   val probeQueue = Module(new ProbeQueue(edge))
   val wb         = Module(new WritebackUnit(edge))
@@ -271,6 +271,26 @@ class DCacheImp(outer: DCache) extends LazyModuleImp(outer) with HasDCacheParame
   mainPipeReqArb.io.in(AtomicsMainPipeReqPort) <> atomicsReplayUnit.io.pipe_req
   mainPipeReqArb.io.in(ProbeMainPipeReqPort)   <> probeQueue.io.pipe_req
 
+  when (missQueue.io.pipe_req.valid) {
+    XSDebug("missQueue ")
+    missQueue.io.pipe_req.bits.dump()
+  }
+
+  when (storeReplayUnit.io.pipe_req.valid) {
+    XSDebug("storeReplayUnit ")
+    storeReplayUnit.io.pipe_req.bits.dump()
+  }
+
+  when (atomicsReplayUnit.io.pipe_req.valid) {
+    XSDebug("atomicsReplayUnit ")
+    atomicsReplayUnit.io.pipe_req.bits.dump()
+  }
+
+  when (probeQueue.io.pipe_req.valid) {
+    XSDebug("probeQueue ")
+    probeQueue.io.pipe_req.bits.dump()
+  }
+
   mainPipe.io.req <> mainPipeReqArb.io.out
 
   missQueue.io.pipe_resp         <> mainPipe.io.miss_resp

src/main/scala/xiangshan/cache/LoadPipe.scala

@@ -168,7 +168,7 @@ class LoadPipe extends DCacheModule
   def dump_pipeline_reqs(pipeline_stage_name: String, valid: Bool,
     req: DCacheWordReq ) = {
       when (valid) {
-        XSDebug("$pipeline_stage_name: ")
+        XSDebug(s"$pipeline_stage_name: ")
         req.dump()
       }
   }

src/main/scala/xiangshan/cache/MainPipe.scala

@@ -503,6 +503,14 @@ class MainPipe extends DCacheModule
   io.amo_resp.valid    := s2_valid && s2_req.source === AMO_SOURCE.U
   io.amo_resp.bits     := resp
 
+  when (io.req.fire()) {
+    io.req.bits.dump()
+  }
+
+  when (io.miss_req.fire()) {
+    io.miss_req.bits.dump()
+  }
+
   when (io.miss_resp.fire()) {
     io.miss_resp.bits.dump()
   }
@@ -515,6 +523,13 @@ class MainPipe extends DCacheModule
     io.amo_resp.bits.dump()
   }
 
+  when (io.wb_req.fire()) {
+    io.wb_req.bits.dump()
+  }
+
+  when (io.lrsc_locked_block.valid) {
+    XSDebug("lrsc_locked_block: %x\n", io.lrsc_locked_block.bits)
+  }
 
   // -------
   // Debug logging functions

src/main/scala/xiangshan/cache/Probe.scala

@@ -49,6 +49,10 @@ class ProbeEntry extends DCacheModule {
     XSDebug("state: %d\n", state)
   }
 
+  when (state =/= s_invalid) {
+    XSDebug("ProbeEntry: state: %d block_addr: %x\n", state, io.block_addr.bits)
+  }
+
   when (state === s_invalid) {
     io.req.ready := true.B
     when (io.req.fire()) {
@@ -124,4 +128,18 @@ class ProbeQueue(edge: TLEdgeOut) extends DCacheModule with HasTLDump
     // for now, we can only deal with ProbeBlock
     assert (io.mem_probe.bits.opcode === TLMessages.Probe)
   }
+
+  // debug output
+  when (io.mem_probe.fire()) {
+    XSDebug("mem_probe: ")
+    io.mem_probe.bits.dump
+  }
+
+  when (io.pipe_req.fire()) {
+    io.pipe_req.bits.dump()
+  }
+
+  when (io.lrsc_locked_block.valid) {
+    XSDebug("lrsc_locked_block: %x\n", io.lrsc_locked_block.bits)
+  }
 }