LoopBuffer: Fix LBredirect bug

src/main/scala/xiangshan/frontend/IFU.scala

@@ -359,7 +359,7 @@ class IFU extends XSModule with HasIFUConst
   }
 
   when(inLoop) {
-    io.icacheReq.valid := if2_flush
+    io.icacheReq.valid := if4_flush
   }.otherwise {
     io.icacheReq.valid := if1_valid && if2_ready
     // io.icacheResp.ready := if3_ready
@@ -410,7 +410,7 @@ class IFU extends XSModule with HasIFUConst
 
   pd.io.in := icacheResp
   when(inLoop) {
-    pd.io.in.mask := loopBuffer.io.out.bits.mask & mask(loopBuffer.io.out.bits.pc)
+    pd.io.in.mask := loopBuffer.io.out.bits.mask & mask(loopBuffer.io.out.bits.pc) // TODO: Maybe this is unnecessary
     // XSDebug("Fetch from LB\n")
     // XSDebug(p"pc=${Hexadecimal(io.loopBufPar.LBResp.pc)}\n")
     // XSDebug(p"data=${Hexadecimal(io.loopBufPar.LBResp.data)}\n")
@@ -445,6 +445,7 @@ class IFU extends XSModule with HasIFUConst
   // io.fetchPacket.valid := if4_valid && !io.redirect.valid
   fetchPacketWire.instrs := if4_pd.instrs
   fetchPacketWire.mask := if4_pd.mask & (Fill(PredictWidth, !if4_bp.taken) | (Fill(PredictWidth, 1.U(1.W)) >> (~if4_bp.jmpIdx)))
+  loopBufPar.noTakenMask := if4_pd.mask
   fetchPacketWire.pc := if4_pd.pc
   (0 until PredictWidth).foreach(i => fetchPacketWire.pnpc(i) := if4_pd.pc(i) + Mux(if4_pd.pd(i).isRVC, 2.U, 4.U))
   when (if4_bp.taken) {

src/main/scala/xiangshan/frontend/NewLoopBuffer.scala

@@ -15,6 +15,7 @@ trait HasLoopBufferCst extends HasXSParameter {
 class LoopBufferParameters extends XSBundle {
   val LBredirect = ValidIO(UInt(VAddrBits.W))
   val fetchReq = Input(UInt(VAddrBits.W))
+  val noTakenMask = Input(UInt(PredictWidth.W))
   // val preFetchPC = DecoupledIO(UInt(VAddrBits.W))
   // val preFetchResp = Flipped(DecoupledIO(new ICacheResp))
   // val preFetchSend = DecoupledIO(new ICacheResp)
@@ -97,7 +98,7 @@ class NewLoopBuffer extends XSModule with HasLoopBufferCst{
 
   // Enque loop body
   when(io.in.fire && LBstate === s_fill) {
-    io.in.bits.mask.asBools().zipWithIndex.map {case(m, i) =>
+    io.loopBufPar.noTakenMask.asBools().zipWithIndex.map {case(m, i) =>
       when(m) {
         buffer(io.in.bits.pc(i)(7,1)).inst := io.in.bits.instrs(i)(15, 0)
         bufferValid(io.in.bits.pc(i)(7,1)) := true.B