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体验新版 GitCode,发现更多精彩内容 >>
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a1d6ade0
编写于
8月 04, 2020
作者:
Z
zhanglinjuan
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电子邮件补丁
差异文件
ifu/bpu: calculate jal target directly
上级
f227c0cc
变更
2
显示空白变更内容
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并排
Showing
2 changed file
with
9 addition
and
3 deletion
+9
-3
src/main/scala/xiangshan/frontend/BPU.scala
src/main/scala/xiangshan/frontend/BPU.scala
+2
-2
src/main/scala/xiangshan/frontend/IFU.scala
src/main/scala/xiangshan/frontend/IFU.scala
+7
-1
未找到文件。
src/main/scala/xiangshan/frontend/BPU.scala
浏览文件 @
a1d6ade0
...
...
@@ -251,12 +251,12 @@ class BPUStage3 extends BPUStage {
}
// predict taken only if btb has a target
takens
:=
VecInit
((
0
until
PredictWidth
).
map
(
i
=>
(
brTakens
(
i
)
||
jal
s
(
i
)
||
jalrs
(
i
))
&&
btbHit
s
(
i
)))
takens
:=
VecInit
((
0
until
PredictWidth
).
map
(
i
=>
(
brTakens
(
i
)
||
jal
rs
(
i
))
&&
btbHits
(
i
)
||
jal
s
(
i
)))
// Whether should we count in branches that are not recorded in btb?
// PS: Currently counted in. Whenever tage does not provide a valid
// taken prediction, the branch is counted as a not taken branch
notTakens
:=
(
if
(
EnableBPD
)
{
VecInit
((
0
until
PredictWidth
).
map
(
i
=>
brs
(
i
)
&&
!
tageValidTakens
(
i
)))}
else
{
VecInit
((
0
until
PredictWidth
).
map
(
i
=>
brs
(
i
)
&&
bimTakens
(
i
)))})
else
{
VecInit
((
0
until
PredictWidth
).
map
(
i
=>
brs
(
i
)
&&
!
bimTakens
(
i
)))})
targetSrc
:=
inLatch
.
resp
.
btb
.
targets
lastIsRVC
:=
pds
(
lastValidPos
).
isRVC
...
...
src/main/scala/xiangshan/frontend/IFU.scala
浏览文件 @
a1d6ade0
...
...
@@ -179,7 +179,12 @@ class IFU extends XSModule with HasIFUConst
.
elsewhen
(
if3_fire
)
{
if4_valid
:=
if3_valid
}
.
elsewhen
(
if4_fire
)
{
if4_valid
:=
false
.
B
}
val
if4_bp
=
bpu
.
io
.
out
(
2
).
bits
val
if4_bp
=
Wire
(
new
BranchPrediction
)
if4_bp
:=
bpu
.
io
.
out
(
2
).
bits
// TODO: c_jal
val
if4_cfi_jal
=
if4_pd
.
instrs
(
if4_bp
.
jmpIdx
)
val
if4_cfi_jal_tgt
=
if4_pd
.
pc
(
if4_bp
.
jmpIdx
)
+
SignExt
(
Cat
(
if4_cfi_jal
(
31
),
if4_cfi_jal
(
19
,
12
),
if4_cfi_jal
(
20
),
if4_cfi_jal
(
30
,
21
),
0.
U
(
1.
W
)),
XLEN
)
if4_bp
.
target
:=
Mux
(
if4_pd
.
pd
(
if4_bp
.
jmpIdx
).
isJal
&&
if4_bp
.
taken
,
if4_cfi_jal_tgt
,
bpu
.
io
.
out
(
2
).
bits
.
target
)
when
(
bpu
.
io
.
out
(
2
).
valid
&&
if4_fire
&&
if4_bp
.
redirect
)
{
when
(!
if4_bp
.
saveHalfRVI
)
{
...
...
@@ -291,6 +296,7 @@ class IFU extends XSModule with HasIFUConst
XSDebug
(
"[IF4][predecode] mask=%b\n"
,
if4_pd
.
mask
)
XSDebug
(
"[IF4][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n"
,
if4_bp
.
redirect
,
if4_bp
.
taken
,
if4_bp
.
jmpIdx
,
if4_bp
.
hasNotTakenBrs
,
if4_bp
.
target
,
if4_bp
.
saveHalfRVI
)
XSDebug
(
if4_pd
.
pd
(
if4_bp
.
jmpIdx
).
isJal
&&
if4_bp
.
taken
,
"[IF4] cfi is jal! instr=%x target=%x\n"
,
if4_cfi_jal
,
if4_cfi_jal_tgt
)
XSDebug
(
io
.
fetchPacket
.
fire
(),
"[IF4][fetchPacket] v=%d r=%d mask=%b\n"
,
io
.
fetchPacket
.
valid
,
io
.
fetchPacket
.
ready
,
io
.
fetchPacket
.
bits
.
mask
)
for
(
i
<-
0
until
PredictWidth
)
{
XSDebug
(
io
.
fetchPacket
.
fire
(),
"[IF4][fetchPacket] %b %x pc=%x pnpc=%x pd: rvc=%d brType=%b call=%d ret=%d\n"
,
...
...
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