From a1d6ade06ef8bb7a7a35557024e70dadbb92afae Mon Sep 17 00:00:00 2001 From: zhanglinjuan Date: Tue, 4 Aug 2020 22:20:49 +0800 Subject: [PATCH] ifu/bpu: calculate jal target directly --- src/main/scala/xiangshan/frontend/BPU.scala | 4 ++-- src/main/scala/xiangshan/frontend/IFU.scala | 8 +++++++- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/src/main/scala/xiangshan/frontend/BPU.scala b/src/main/scala/xiangshan/frontend/BPU.scala index f3049c280..58616e515 100644 --- a/src/main/scala/xiangshan/frontend/BPU.scala +++ b/src/main/scala/xiangshan/frontend/BPU.scala @@ -251,12 +251,12 @@ class BPUStage3 extends BPUStage { } // predict taken only if btb has a target - takens := VecInit((0 until PredictWidth).map(i => (brTakens(i) || jals(i) || jalrs(i)) && btbHits(i))) + takens := VecInit((0 until PredictWidth).map(i => (brTakens(i) || jalrs(i)) && btbHits(i) || jals(i))) // Whether should we count in branches that are not recorded in btb? // PS: Currently counted in. Whenever tage does not provide a valid // taken prediction, the branch is counted as a not taken branch notTakens := (if (EnableBPD) { VecInit((0 until PredictWidth).map(i => brs(i) && !tageValidTakens(i)))} - else { VecInit((0 until PredictWidth).map(i => brs(i) && bimTakens(i)))}) + else { VecInit((0 until PredictWidth).map(i => brs(i) && !bimTakens(i)))}) targetSrc := inLatch.resp.btb.targets lastIsRVC := pds(lastValidPos).isRVC diff --git a/src/main/scala/xiangshan/frontend/IFU.scala b/src/main/scala/xiangshan/frontend/IFU.scala index e270456db..feb7d92cb 100644 --- a/src/main/scala/xiangshan/frontend/IFU.scala +++ b/src/main/scala/xiangshan/frontend/IFU.scala @@ -179,7 +179,12 @@ class IFU extends XSModule with HasIFUConst .elsewhen (if3_fire) { if4_valid := if3_valid } .elsewhen(if4_fire) { if4_valid := false.B } - val if4_bp = bpu.io.out(2).bits + val if4_bp = Wire(new BranchPrediction) + if4_bp := bpu.io.out(2).bits + // TODO: c_jal + val if4_cfi_jal = if4_pd.instrs(if4_bp.jmpIdx) + val if4_cfi_jal_tgt = if4_pd.pc(if4_bp.jmpIdx) + SignExt(Cat(if4_cfi_jal(31), if4_cfi_jal(19, 12), if4_cfi_jal(20), if4_cfi_jal(30, 21), 0.U(1.W)), XLEN) + if4_bp.target := Mux(if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken, if4_cfi_jal_tgt, bpu.io.out(2).bits.target) when (bpu.io.out(2).valid && if4_fire && if4_bp.redirect) { when (!if4_bp.saveHalfRVI) { @@ -291,6 +296,7 @@ class IFU extends XSModule with HasIFUConst XSDebug("[IF4][predecode] mask=%b\n", if4_pd.mask) XSDebug("[IF4][bp] redirect=%d taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n", if4_bp.redirect, if4_bp.taken, if4_bp.jmpIdx, if4_bp.hasNotTakenBrs, if4_bp.target, if4_bp.saveHalfRVI) + XSDebug(if4_pd.pd(if4_bp.jmpIdx).isJal && if4_bp.taken, "[IF4] cfi is jal! instr=%x target=%x\n", if4_cfi_jal, if4_cfi_jal_tgt) XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] v=%d r=%d mask=%b\n", io.fetchPacket.valid, io.fetchPacket.ready, io.fetchPacket.bits.mask) for (i <- 0 until PredictWidth) { XSDebug(io.fetchPacket.fire(), "[IF4][fetchPacket] %b %x pc=%x pnpc=%x pd: rvc=%d brType=%b call=%d ret=%d\n", -- GitLab