backend: remove lsrc usages after rename (#1124)

This commit removes lsrc usages in the fence unit and lsrc is no longer
needed after an instruction is renamed. It helps timing and area.

lsrc is placed in imm at rename stage (the last stage we need lsrc).
They are extracted in the fence unit. Imm needs to go through the
pipelines because Jump needs it (and we re-use it for lsrc).

.github/workflows/check_verilog.py

@@ -7,17 +7,23 @@ def err(line, loc, msg):
     exit(1)
 
 if __name__ == "__main__":
-    in_module = False
+    in_decode = False
+    in_dispatch = False
     line_number = 0
     with open(sys.argv[1], "r") as f:
         for line in f:
             if "$fatal" in line or "$fwrite" in line:
                 err(line, line_number, "'fatal' or 'fwrite' statement was found!")
             if "module Decode" in line:
-                in_module = True
+                in_decode = True
+            elif "module Dispatch" in line:
+                in_dispatch = True
             elif "endmodule" in line:
-                in_module = False
-            elif in_module and "_pc" in line:
+                in_decode = False
+                in_dispatch = False
+            elif in_decode and "_pc" in line:
                 err(line, line_number, "PC should not be in decode!!!\n")
+            elif in_dispatch and "_lsrc" in line:
+                err(line, line_number, "lsrc should not be in dispatch!!!\n")
             line_number += 1
     exit(0)

src/main/scala/xiangshan/backend/dispatch/Dispatch2Rs.scala

@@ -184,7 +184,6 @@ class Dispatch2RsDistinctImp(outer: Dispatch2Rs)(implicit p: Parameters) extends
         io.out(idx).valid := selectValid && sta.ready
         sta.valid := selectValid && io.out(idx).ready
         io.out(idx).bits.ctrl.srcType(0) := Mux1H(selectIdxOH, io.in.map(_.bits.ctrl.srcType(1)))
-        io.out(idx).bits.ctrl.lsrc(0) := Mux1H(selectIdxOH, io.in.map(_.bits.ctrl.lsrc(1)))
         io.out(idx).bits.psrc(0) := Mux1H(selectIdxOH, io.in.map(_.bits.psrc(1)))
         io.in.zip(selectIdxOH).foreach{ case (in, v) => when (v) { in.ready := io.out(idx).ready && sta.ready }}
         XSPerfAccumulate(s"st_rs_not_ready_$idx", selectValid && (!sta.ready || !io.out(idx).ready))

src/main/scala/xiangshan/backend/fu/Fence.scala

@@ -34,11 +34,6 @@ class Fence(implicit p: Parameters) extends FunctionUnit with HasExceptionNO {
   val toSbuffer = IO(new FenceToSbuffer)
   val disableSfence = IO(Input(Bool()))
 
-  val (valid, src1) = (
-    io.in.valid,
-    io.in.bits.src(0)
-  )
-
   val s_idle :: s_wait :: s_tlb :: s_icache :: s_fence :: Nil = Enum(5)
   val state = RegInit(s_idle)
   /* fsm
@@ -58,11 +53,13 @@ class Fence(implicit p: Parameters) extends FunctionUnit with HasExceptionNO {
   sbuffer      := state === s_wait && !(func === FenceOpType.sfence && disableSfence)
   fencei       := state === s_icache
   sfence.valid := state === s_tlb && !disableSfence
-  sfence.bits.rs1  := uop.ctrl.lsrc(0) === 0.U
-  sfence.bits.rs2  := uop.ctrl.lsrc(1) === 0.U
-  sfence.bits.addr := RegEnable(src1, io.in.fire())
+  sfence.bits.rs1  := uop.ctrl.imm(4, 0) === 0.U
+  sfence.bits.rs2  := uop.ctrl.imm(9, 5) === 0.U
+  XSError(sfence.valid && uop.ctrl.lsrc(0) =/= uop.ctrl.imm(4, 0), "lsrc0 is passed by imm\n")
+  XSError(sfence.valid && uop.ctrl.lsrc(1) =/= uop.ctrl.imm(9, 5), "lsrc1 is passed by imm\n")
+  sfence.bits.addr := RegEnable(io.in.bits.src(0), io.in.fire())
 
-  when (state === s_idle && valid) { state := s_wait }
+  when (state === s_idle && io.in.valid) { state := s_wait }
   when (state === s_wait && func === FenceOpType.fencei && sbEmpty) { state := s_icache }
   when (state === s_wait && func === FenceOpType.sfence && (sbEmpty || disableSfence)) { state := s_tlb }
   when (state === s_wait && func === FenceOpType.fence  && sbEmpty) { state := s_fence }
@@ -74,7 +71,7 @@ class Fence(implicit p: Parameters) extends FunctionUnit with HasExceptionNO {
   io.out.bits.uop := uop
   io.out.bits.uop.cf.exceptionVec(illegalInstr) := func === FenceOpType.sfence && disableSfence
 
-  XSDebug(valid, p"In(${io.in.valid} ${io.in.ready}) state:${state} Inpc:0x${Hexadecimal(io.in.bits.uop.cf.pc)} InrobIdx:${io.in.bits.uop.robIdx}\n")
+  XSDebug(io.in.valid, p"In(${io.in.valid} ${io.in.ready}) state:${state} Inpc:0x${Hexadecimal(io.in.bits.uop.cf.pc)} InrobIdx:${io.in.bits.uop.robIdx}\n")
   XSDebug(state =/= s_idle, p"state:${state} sbuffer(flush:${sbuffer} empty:${sbEmpty}) fencei:${fencei} sfence:${sfence}\n")
   XSDebug(io.out.valid, p" Out(${io.out.valid} ${io.out.ready}) state:${state} Outpc:0x${Hexadecimal(io.out.bits.uop.cf.pc)} OutrobIdx:${io.out.bits.uop.robIdx}\n")
 

src/main/scala/xiangshan/backend/rename/Rename.scala

@@ -149,6 +149,9 @@ class Rename(implicit p: Parameters) extends XSModule {
 
     io.out(i).valid := io.in(i).valid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && !io.robCommits.isWalk
     io.out(i).bits := uops(i)
+    when (io.out(i).bits.ctrl.fuType === FuType.fence) {
+      io.out(i).bits.ctrl.imm := Cat(io.in(i).bits.ctrl.lsrc(1), io.in(i).bits.ctrl.lsrc(0))
+    }
 
     // write speculative rename table
     // we update rat later inside commit code